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W925EP01/ W925EP01FG 8-BIT CID MICROCONTROLLER
Table of Contents1. 2. 3. 4. 5. 6. GENERAL DESCRIPTION ......................................................................................................... 2 FEATURES ................................................................................................................................. 2 PIN CONFIGURATION ............................................................................................................... 4 PIN DESCRIPTION..................................................................................................................... 5 BLOCK DIAGRAM ...................................................................................................................... 7 FUNCTIONAL DESCRIPTION ................................................................................................. 10 6.1 Memory Organization ................................................................................................... 11 6.2 Special Function Registers ........................................................................................... 14 6.3 Initial State of Registers................................................................................................ 41 6.4 Instruction ..................................................................................................................... 42 6.5 Power Management...................................................................................................... 45 6.6 Reset............................................................................................................................. 46 6.7 Interrupt......................................................................................................................... 47 6.8 Programmable Timers/Counters .................................................................................. 50 6.9 Serial Port ..................................................................................................................... 54 6.10 Comparator ................................................................................................................... 61 6.11 DTMF Generator........................................................................................................... 62 6.12 FSK Generator.............................................................................................................. 63 6.13 CAS Generator ............................................................................................................. 64 6.14 I/O Ports........................................................................................................................ 65 6.15 Divider........................................................................................................................... 66 6.16 Timed Access Protection .............................................................................................. 66 6.17 Hardware Writer Mode.................................................................................................. 68 6.18 In-System Programming (ISP) Mode............................................................................ 68 6.19 Security Bits .................................................................................................................. 81 6.20 Calling Identity Delivery (CID)....................................................................................... 83 TIMING WAVEFORMS ............................................................................................................. 97 7.1 Instruction Timing ......................................................................................................... 98 ELECTRICAL CHARACTERISTICS....................................................................................... 101 8.1 Maximum Ratings*...................................................................................................... 101 8.2 Recommended Operating Conditions ........................................................................ 101 8.3 DC Electrical Characteristics ...................................................................................... 102 8.4 Electrical Characteristics - Gain Control OP-Amplifier ............................................... 104 8.5 AC Electrical Characteristics ...................................................................................... 104 PACKAGE ............................................................................................................................... 107 REVISION HISTORY .............................................................................................................. 108
7. 8.
9. 10.
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
1. GENERAL DESCRIPTION
The W925EP01 is an all in one single 8-bit micro-controller with widely used Calling Identity Delivery (CID) function. The 8-bit CPU core is based on the 8051-family; therefore, all the instructions are compatible to the Turbo 8051 series. That contains a 64K bytes of main Flash EPROM (APROM) and a 4K bytes of auxiliary Flash EPROM (LDROM) which allows the contents of the 64KB main Flash EPROM (APROM) to be updated by the loader program located at the 4KB auxiliary Flash EPROM (LDROM). W925EP01 can be extend to two 64KB program banks, there are APROM (00000H~0FFFFH) and external program ROM (10000H~1FFFFH), user can access the external ROM by P5, P6, P7, A16 and PSEN . All instructions are fetched for execution from this memory areas, the MOVC instruction can also access the external memory regions. The CID part consisted of FSK decoder, DTMF receiver, CPE* Alert Signal (CAS) detector and Ring detector. Also are built-in DTMF generator, FSK generator with baud rate 1200 bps (bits/sec) and CAS generator. Using W925EP01 can easily implement the CID adjunct box and the feature phone or Short Message Service (SMS) phone with CID function. The main features are listed in the next section.
2. FEATURES
* CPU: 8-bit micro-controller is similar to the 8051 family. - Flash EPROM type (E version) operating voltage: C: The C operating voltage is from 2.4 to 5.5V. The ISP operating voltage is from 3.3 to 5.5V. CID: The CID receiver operating voltage is from 3.0 to 5.5V. * Dual-clock operation: - Main oscillator: Connect with 4M/8MHz crystal, built-in RC oscillator for clock stable from main crystal wake up. - Sub oscillator: connect with 32768Hz crystal. - Main and sub oscillators are enabled/disabled by bit control individually. * ROM: - 64K bytes of in-system-programmable Flash EPROM for application program (APROM). - 4K bytes of auxiliary Flash EPROM for loader program (LDROM). - 64K bytes external program memories address space. * RAM: - 256 bytes on chip scratch pad RAM. - 4K bytes on chip RAM for MOVX instruction. - 64K bytes external data memories address space. * CID - Compatible with Bellcore TR-NWT-000030 & SR-TSV-002476, British Telecom (BT) SIN227, U.K. Cable Communication Association (CCA) specification. - FSK modulator/demodulator: for Bell 202 and ITU-T V.23 FSK with 1200-baud rate. - CAS generator/detector: for dual tones of Bellcore CAS and BT Idle State and Loop State Dual Tone Alert Signal (DTAS). - DTMF generator/receiver; DTMF receiver can be programmed as a tone detector. - Ring detector: for line reversal for BT, ring burst for CCA or ring signal for Bellcore. - Two independent OP amps with adjustable gain for Tip/Ring and Telephone Hybrid connections.
Note: "CPE*" Customer Premises Equipment
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W925EP01/ W925EP01FG
* I/O: 64 I/O pins. - P0: Bit and byte addressable. I/O mode can be bit controlled. Open drain type. - P1~P3: Bit and byte addressable. Pull high and I/O mode can be bit controlled. - P4: Byte addressable. Pull high and I/O mode can be bit controlled. - P5~P6: Byte addressable. Pull high and I/O mode can be bit controlled, P5~P6 also provide the address bus A0~A15 for access external program memory or data memory. - P7: Byte addressable. Pull high and I/O mode can be bit controlled, P7 also provide the data bus D0~D7 for access external program memory or data memory * Power mode: - Normal mode: Normal operation. - Dual-clock slow operation mode: System is operated from the sub-oscillator. (Fosc=Fs and Fm is stopped) - Idle mode: CPU hold. The clock to the CPU is halted, but the interrupt, timer and watchdog timer block work normally but CID function is disabled. - Power down mode: All activity is completely stopped and power consumption is less than 1uA. * Timer: Dual 13/16-bit timers or 8-bit auto-reload timers, that are Timer0 and Timer1. * Watchdog timer: WDT can be programmed by the user to serve as a system monitor. * Interrupt: 12 interrupt sources with two levels of priority. - 4 interrupts from INT0, INT1, INT2 and INT3. - 2 interrupts from Timer0 and Timer1. - 2 interrupt from Serial port0 and Serial port1. - 1 interrupt from CID. - 1 interrupt from 13/14-bit Divider. - 1 interrupt from Comparator. - 1 interrupt from Watch Dog Timer. * Divider: 13/14bit divider, clock source from sub-oscillator. Therefore, DIVF set every 0.25/0.5 second. * Comparator: - Comparator: 1 analog input from VNEG pin. 1 reference input from VPOS pin. * Serial ports: - Serial port0: One full duplex serial port. (UART) - Serial port1: An 8-bit serial transceiver with SCLK1 and SDATA1. (Serial interface port) * Package: - 100pin QFP: W925EP01 - 100pin lead-free QFP: W925EP01FG
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
3. PIN CONFIGURATION
shows the pin assignment. The package type is 100pin QFP.
U?
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
RESET EA BUZ P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 P37/RD P36/WR P35/T1 P34/T0 P33/INT1 P32/INT0 P31/TxD P30/RxD P47 P46 P45
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
XOUT2 XIN2 VDD TEST XIN1 XOUT1 VSS P70/D0 P71/D1 P72/D2 P73/D3 P74/D4 P75/D5 P76/D6 P77/D7 NC NC NC NC NC
W925EP01
P44/VPOS P43 P42/VNEG P41/SDATA1 P40/SCLK1 DTMF/FSK RNGDI RNGRC NC NC INP2 INN2 GCFB2 VAS VAD GCFB1 INN1 INP1 VREF CAP
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
W925EP01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P50/A0 P51/A1 P52/A2 P53/A3 P54/A4 P55/A5 P56/A6 P57/A7 P60/A8 P61/A9 P62/A10 P63/A11 P64/A12 P65/A13 P66/A14 P67/A15 A16 PSEN P00 P01 P02 P03 P04 P05 P06 P07 TEST1 NC NC NC
Figure 3-1 W925EP01 Pin Configuration
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W925EP01/ W925EP01FG
4. PIN DESCRIPTION
SYMBOL I/O FUNCTION
RNGDI
I
Ring Detect Input (Schmitt trigger input). Used for ring detection and line reversal detection. Must maintain a voltage between VAD and VAS. Ring RC (Open drain output and Schmitt trigger input). Used to set the time interval from the end of RNGDI pin to the inactive condition of the RNGON pin. An external resistor must be connected to VAD and a capacitor connected to VSS, the time interval is the RC time constant. Must be connected 0.1uF capacitor to VSS. Reference Voltage. Nominally, VDD/2 is used to bias the input of the gain control op-amp. Op-amp1 Feed-back Gain Control signal. Select the input gain by connecting this pin and the INN1 pin with feedback resistor. It is recommended that the op-amp1 be set to unity gain. Inverting Input of the gain control op-amp1. Non-inverting Input of the gain control op-amp1. Op-amp2 Feed-back Gain Control signal. Select the input gain by connecting this pin and the INN2 pin with feedback resistor. It is recommended that the op-amp2 be set to unity gain. Inverting Input of the gain control op-amp2. Non-inverting Input of the gain control op-amp2. Analog voltage supply. Analog ground. Digital voltage supply. Digital ground. Output pin for main-oscillator. Connected to 4M/8MHz crystal for CID function. Input pin for main-oscillator. Connected to 4M/8MHz crystal for CID function. Output pin for sub-oscillator. Connected to 32.768KHz crystal only. Suggest to add an external capacitor about 10~30pF to ground (VSS) for the accuracy of the oscillator. Input pin for sub-oscillator. Connected to 32.768KHz crystal only. Suggest to add an external capacitor about 10~30pF to ground (VSS) for the accuracy of the oscillator. EXTERNAL ACCESS ENABLE. Set high for normal function. Set low for external mode running; P5~P6/A0~A15 and A16 are external address bus, P7/D0~D7 are external data bus, and PSEN pin is always emits pulses during access to external ROM. This pin with internal pull-high resistor.
RNGRC CAP VREF GCFB1 INN1 INP1 GCFB2 INN2 INP2 VAD VAS VDD VSS XOUT1 XIN1 XOUT2
O O O O I I O I I I I I I O I O
XIN2
I
EA
I
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
Pin Description, continued
SYMBOL
I/O
FUNCTION
RESET BUZ
I O
RESET pin. A high pulse causes the whole chip reset. This pin with internal pull-low resistor. Buzzer output pin. If buzzer function is disabled, BUZ pin is kept in floating state. DTMFG=1, CASGE=FTE=0, Dual-Tone Multi-Frequency (DTMF) signal output.
DTMF
O
FTE=1, CASGE=DTMFG=0, FSK signal output. CASGE=1, FTE=DTMF=0, CAS signal output. For signal send to the DTMF pin, CAS has the first priority, FSK has the second priority, and DTMF has the third priority. Input/output port0. Port0 data can be bit controlled. The I/O mode is controlled by P0IO register. Port0 is open drain type when it is configured as output mode. Input/output port1 with pull high resistors. Port1 data can be bit controlled. The I/O mode is controlled by P1IO register. The P10-P13 and P14-P17 indicate the external interrupt pins. (INT2 and INT3) Input/output port2 with pull high resistors. Port2 data can be bit controlled. The I/O mode is controlled by P2IO register. Input/output port3 with pull high resistors. Port3 data can be bit controlled. The I/O mode is controlled by P3IO register. The special function of port3 is referred to the description of P3 register. Contents are byte controlled. Pull high and I/O mode can be bit controlled. The special function of P4 is referred to the description of P4 register. The comparator analog input pins V- and V+, share with P4.2 (VNEG) and P4.4 (VPOS) pins. Contents are byte controlled. Pull high and I/O mode can be bit controlled. The special function of P5 is referred to the description of P5 register. P5 outputs the address <7:0> of the external program ROM multiplexed with the address <7:0> of the external data RAM. Contents are byte controlled. Pull high and I/O mode can be bit controlled. The special function of P6 is referred to the description of P6 register. P6 outputs the address <7:0> of the external program ROM multiplexed with the address <15:8> of the external data RAM. During the execution of "MOVX @Ri", the output of P6 comes from the HB register, which is the high byte address, and its address is 0A1H. Contents are byte controlled. Pull high and I/O mode can be bit controlled. The special function of P7 is referred to the description of P7 register. P7 inputs the data <7:0> of the external ROM. Or, P7 inputs/outputs the data <7:0> of the external data RAM. Test pin. This pin has the built-in pull low resistor. Test pin, This pin must be fixed to VDD. PROGRAM STORE ENABLE. This pin always emits pulses during access to external program ROM.
P00-P07
I/O
P10-P17 P20-P27 P30-P37
I/O I/O I/O
P40-P47
I/O
P50-P57
I/O
P60-P67
I/O
P70-P77 TEST TEST1
PSEN
I/O I I O
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W925EP01/ W925EP01FG
5. BLOCK DIAGRAM
Internal CID and uC interface signals
RNGDI RNGRC INP1 INN1 GCFB1 INP2 INN2 GCFB2 VREF CAP CIDE FSKE CASE P0 P1 P2 P3 P4 P5 P6 P7
8 8 8 8 8 8 8 8 DCLK FD7~FD0 Fosc RNG ALGO FDR FCD CASH,CASL CASPT CASAT DCLK S to P DATA F Reset M
FSK,CAS (W91031)
DTMFD DTMFPT DTMFAT DTMFE
DTMF RECEIVER
DTMFH DTMFL
DD3~DD0
FDATA
D-latch
ck
RNGF ALGOF FDRF DTMFDF FSF
8-bit C
FSK modulator
X I N 1
X O U T 1
X I N 2
X O U T 2
VV AA DS
V D D
V S S
/ E A
P S T N
A 1 6
B U Z
D T M F
R E S E T
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
NORMAL MODE WITH EXTERNAL 64KB PROGRAM ROM AND 64KB EXTERNAL DATA RAM:
10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 20 22 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 U9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE OE 27512 O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19
VCC
U17 32768 VCC X2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
4MHz X1
XOUT2 XIN2 VDD TEST XIN1 XOUT1 VSS P70/D0 P71/D1 P72/D2 P73/D3 P74/D4 P75/D5 P76/D6 P77/D7 NC NC NC NC NC
RESET EA BUZ P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 P37/RD P36/WR P35/T1 P34/T0 P33/INT1 P32/INT0 P31/TxD P30/RxD P47 P46 P45 P44/VPOS P43 P42/VNEG P41/SDATA1 P40/SCLK1 DTMF/FSK RNGDI RNGRC NC NC INP2 INN2 GCFB2 VAS VAD GCFB1 INN1 INP1 VREF CAP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
W925EP01
P50/A0 P51/A1 P52/A2 P53/A3 P54/A4 P55/A5 P56/A6 P57/A7 P60/A8 P61/A9 P62/A10 P63/A11 P64/A12 P65/A13 P66/A14 P67/A15 A16 PSEN P00 P01 P02 P03 P04 P05 P06 P07 TEST1 NC NC NC
U10A
2
VCC
12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 22 30 24 29
U8 A0 A1 A2 A3 A4 A5 A6 A7 A8 32- pin A9 600 mil A10 DIP A11 A12 A13 A14 A15 /CS1 CS2 /OE /WE W24512 D0 D1 D2 D3 D4 D5 D6 D7
13 14 15 17 18 19 20 21
VCC 32 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
W925EP01
VDD VSS
7404
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1
W925EP01/ W925EP01FG
EXTERNAL MODE WITH EXTERNAL 128KB PROGRAM ROM AND 64KB EXTERNAL DATA RAM:
12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 1 31 VCC 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 22 30 24 29 U7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CE OE VPP PGM 27010 U8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 /CS1 CS2 /OE /WE W24512 D0 D1 D2 D3 D4 D5 D6 D7 32- pin 600 mil DIP VCC 32 16 O0 O1 O2 O3 O4 O5 O6 O7 13 14 15 17 18 19 20 21
U16 32768 VCC X2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
RESET EA BUZ P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 P37/RD P36/WR P35/T1 P34/T0 P33/INT1 P32/INT0 P31/TxD P30/RxD P47 P46 P45
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
4MHz X1
XOUT2 XIN2 VDD TEST XIN1 XOUT1 VSS P70/D0 P71/D1 P72/D2 P73/D3 P74/D4 P75/D5 P76/D6 P77/D7 NC NC NC NC NC
W925EP01
P44/VPOS P43 P42/VNEG P41/SDATA1 P40/SCLK1 DTMF/FSK RNGDI RNGRC NC NC INP2 INN2 GCFB2 VAS VAD GCFB1 INN1 INP1 VREF CAP
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
13 14 15 17 18 19 20 21
P50/A0 P51/A1 P52/A2 P53/A3 P54/A4 P55/A5 P56/A6 P57/A7 P60/A8 P61/A9 P62/A10 P63/A11 P64/A12 P65/A13 P66/A14 P67/A15 A16 PSEN P00 P01 P02 P03 P04 P05 P06 P07 TEST1 NC NC NC
VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
W925EP01
VDD VSS
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
6. FUNCTIONAL DESCRIPTION
The W925EP01 is an 8-bit micro-controller with CID function. The 8-bit micro-control has the same instruction set as the 8051 family, with one addition: DEC DPTR (op-code A5H, the DPTR is decreased by 1). In addition, the W925EP01 contains on-chip 4K bytes MOVX RAM. ROM: The W925EP01 contains 64K bytes of main Flash EPROM (APROM) and a 4K bytes of auxiliary Flash EPROM which allows the contents of the 64KB main Flash EPROM to be updated by the loader program located at the 4KB auxiliary Flash EPROM. The 64K bytes of in-system programmable Flash EPROM is for Application Program (APROM). The 4K bytes of auxiliary Flash EPROM are for Loader Program (LDROM). On-chip Data RAM: The W925EP01 has 4K bytes of normal RAM which address is from 000H to FFFH. It only can be accessed by MOVX instruction; this on-chip RAM is optional under software control. The on-chip data RAM is not used for executable program memory. There is no conflict or overlap among the 256 bytes scratchpad RAM and the 4K bytes MOVX SRAM as they use different addressing modes and separate instructions. The on-chip MOVX SRAM will be enabled by set the DME0 bit in the PMR register. After a reset, the DME0 bit is set such that on-chip MOVX SRAM is enabled, and all MOVX data access to internal memory spaces is from 000H to FFFH. CID: The CID functions include the FSK decoder, CAS detector, and DTMF decoder and ring detector. FSK modulator: Support ITU-T V.23 and Bellcore 202 FSK transmit modulated signal to DTMF pin. CAS modulator: W925EP01 provides a CAS generator, which outputs the CAS signal to the DTMF pin. DTMF modulator: The W925EP01 is built-in a dual tone multi-frequency generator, the signal output to DTMF pin. Eight I/O Ports: The W925EP01 has eight 8-bit I/O ports giving 64 lines (Port0 to Port7). Port0 to Port3 can be used as an 8-bit general I/O port with bit-addressable; Port4 to Port7 can be used as an 8-bit general I/O port with byte-addressable. The I/O mode of each port is controlled by PxIO registers. Port1 to Port7 have internal pull high resistors enabled/disabled by PxH registers. Port0 is open-drain type in output mode.
TWO SERIAL I/O PORT:
The W925EP01 has two serial ports. The serial port0, through P3.0 (RxD) and P3.1 (TxD), is similar to the serial port of the original 8051 family. The serial port1, through P4.0 (SCLK1) and P4.1 (SDATA1), is an 8-bit synchronous serial I/O interface. The serial port0 have the enhanced features of Automatic Address recognition and Frame Error detection.
TWO TIMERS, WATCH DOG TIMER AND DIVIDER:
The W925EP01 has two 13/16-bit timers or 8-bits auto-reload timers. An independent watchdog timer is used as a system monitor or as a very long time period timer. A divider can produce the divider interrupt in every period of 0.5S or 0.25S. Comparator: The W925EP01 has an internal comparator with one external analog signal input path VNEG (P4.2) and an external reference input path VPOS (P4.4).
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W925EP01/ W925EP01FG
Interrupts: The W925EP01 provides 12 interrupt resources with two priority levels, including 4 external interrupt sources, 2 timer interrupts, 1 CID interrupt, 1 divider interrupt, 2 serial port interrupt, 1 comparator interrupt and 1 watchdog timer interrupt. Power Management: The W925EP01 has IDLE and POWER DOWN modes of operation. In the IDLE mode, the clock to the CPU core is stopped however the functions of the timers, divider, CID and interrupts are active continuously. In the POWER DOWN mode, both of the system clocks stop oscillating and the chip operation is completely stopped. POWER DOWN mode is the state of the lowest power consumption.
6.1
Memory Organization
The W925EP01 separates the memory into two separate sections, the Program Memory and the Data Memory. The Program Memory is used to store the instruction op-codes and look-up table data, while the Data Memory is used to store data or for memory mapped devices. Program Memory: The W925EP01 is an 8-bit micro controller which has an in-system programmable EPROM for firmware updating. The instruction set of the W925EP01 is fully compatible with the standard 8052. The W925EP01 contains a 64K bytes of main EPROM and a 4K bytes of auxiliary Flash EPROM which allows the contents of the 64KB main EPROM to be updated by the loader program located at the 4KB auxiliary Flash EPROM. To facilitate programming and verification, the EPROM inside the W925EP01 allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The Program Memory on the W925EP01 can be up to 128K bytes. That is 64K bytes of on chip insystem programmable Flash EPROM (APROM) for Application Program and 64K bytes of external program ROM for code or data memory expansion. The 4K bytes of auxiliary Flash EPROM (LDROM) are for Loader Program. The whole 128K can be used to store look-up table data. Because the op-code is 64K addressable, a PG bit in PAGE register decides which ROM page between page0, page1 is enabled, and the ALU fetches the op-code from the selected ROM page. If PG=0, ALU fetches the op-code from page0. If PG=1, ALU fetches the op-code from page1. When MOVC instruction is executed, ALU fetches the look-up table data according the indication of LT bits. The value of LT indicates which ROM page is active for look-up table instruction.
1FFFF 64K External Program ROM Page1 64K APROM Page0 00000 PG=1 LT=1
10000 0FFFF
PG=0
LT=0
FFF 000
4K LDROM
Figure 6-1 Program Memory Map
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
Data Memory: The W925EP01 contains on-chip 4K MOVX RAM of Data Memory, which can only be accessed by MOVX instructions from the address 000H to FFFH. Access to the on-chip MOVX SRAM is optional by software setting DME0 to "1", MOVX addresses greater than FFFH automatically go to external memory through A0 to A15; this is the default condition. When DME0 be clearing to "0", the 4K data memory area is transparent to the system memory map. Any MOVX directed to the space between 0000H to FFFFH goes to expanded bus on A0 to A15. In addition, the W925EP01 has 256 bytes of on-chip scratchpad RAM. This can be accessed either by direct addressing or by indirect addressing. There are also Special Function Registers (SFRs), which can only be accessed by direct addressing. Since the scratchpad RAM is only 256 bytes, it can be used only when data contents are small. In the event that larger data contents are present, the only one selection is external data memory. However, the on-chip RAM has the fastest access times. The memory map is shown Figure 6-2 and Figure 6-3 shows the scratched-pad RAM/register addressing.
FFFFH
FFH 80H 7FH 00H
Indirect Addressing RAM Direct & Indirect Addressing RAM
SFRs Direct Addressing only 64K bytes External Data Memory
FFFH
4K byte On-chip SRAM
0000H
0000H
Figure 6-2 Data Memory Map
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W925EP01/ W925EP01FG
FFh 80h 7Fh 30h 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 1Fh 18h 17h 10h 0Fh 08h 07h 00h
Indirect RAM Direct RAM
7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 Bank 3 Bank 2 Bank 1 Bank 0 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00
Bit Addressable 20H- 2FH
Figure 6-3 Scratchpad RAM/Register Addressing
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
6.2 Special Function Registers
The W925EP01 uses Special Function Registers (SFRs) to control and monitor peripherals and their Modes. The SFRs reside in the register locations 80-FFh and accessed by direct addressing only. Some of the SFRs are bit addressable. This is very useful in cases where one wishes to modify a particular bit without changing the others. The SFRs that are bit addressable are those whose addresses end in 0 or 8. The list of SFRs is as follows. The table is condensed with eight locations per row. Empty locations indicate that there are no registers at these addresses. The content of reserved bits or registers is not guaranteed. Table 1 Special Function Register Location Table F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 EIP B EIE ACC WDCON PSW DIVC SCON1 IP P3 IE P2 SCON P1 TCON P0 HB SBUF EXIF TMOD SP RPAGE TL0 DPL CIDR SBUF1 REGVC DTMFG CIDFG P6H P4H COMPR CIDPCR P7H P5H P1EF P1SR TL1 DPH P0IO TH0 DPL1 PMR IRC1 FSKDR P7IO P7 STATUS IRC2 BGCON FSKTC CASPT BG FSKTB CASAT SFRAL SFRAH TA SFRFD CHPCO N SFRCN CIDGD CIDGA FF F7 EF E7 DF D7 CF C7 BF
DTMFDR DTMFPT P6IO P6 P1H P1IO TH1 DPH1 P4IO P4 P2H P2IO
DTMFAT B7 P5IO P5 P3H P3IO AF A7 9F 97
CKCON1 CKCON2 8F DPS PCON 87
Note: The SFRs in the column with dark borders are bit-addressable.
A brief description of the SFRs now follows. PORT 0 Bit: 7 P0.7 Mnemonic: P0 6 P0.6 5 P0.5 4 P0.4 3 P0.3 (initial=FFH) 2 P0.2 1 P0.1 0 P0.0
Address: 80h
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W925EP01/ W925EP01FG
P0: P0 can be selected as input or output mode by the P0IO register. At initial reset, P0IO is set to FFH, P0 is used as input mode. When P0IO is set to 0, the P0 is used as CMOS open drain mode. (initial=07H) Bit: 7 SP.7 Mnemonic: SP SP: 6 SP.6 5 SP.5 4 SP.4 3 SP.3 2 SP.2 1 SP.1 0 SP.0
STACK POINTER
Address: 81h
The Stack Pointer stores the scratchpad RAM address where the stack begins. In other words, it always points to the top of the stack.
DATA POINTER LOW Bit: 7 DPL.7 Mnemonic: DPL DPL: This is the low byte of the standard 8052 16-bit data pointer. DATA POINTER HIGH Bit: 7 DPH.7 Mnemonic: DPH DPH: This is the high byte of the standard 8052 16-bit data pointer. DATA POINTER LOW1 Bit: 7 6 5 4 3 6 DPH.6 5 DPH.5 4 DPH.4 3 DPH.3 6 DPL.6 5 DPL.5 4 DPL.4 3 DPL.3
(initial=00H) 2 DPL.2 1 DPL.1 0 DPL.0
Address: 82h
(initial=00H) 2 DPH.2 1 DPH.1 0 DPH.0
Address: 83h
(initial=00H) 2 1 0
DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0 Mnemonic: DPL1 DPL1: Address: 84h
This is the low byte of the new additional 16-bit data pointer. That has been added to the W925EP01. The user can switch between DPL, DPH and DPL1, DPH1 simply by setting register DPS.0 = 1. The instructions that use DPTR will now access DPL1 and DPH1 in place of DPL and DPH. If they are not required, they used as conventional register locations by the user. (initial=00H) 7 6 5 4 3 2 1 0
DATA POINTER HIGH1 Bit:
DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 Mnemonic: DPH1 Address: 85h Publication Release Date: Apr. 10, 2006 Revision A2
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W925EP01/ W925EP01FG
DPH1: This is the high byte of the new additional 16-bit data pointer. That has been added to the W925EP01. The user can switch between DPL, DPH and DPL1, DPH1 simply by setting register DPS = 1. The instructions that use DPTR will now access DPL1 and DPH1 in place of DPL and DPH. If they are not required, they used as conventional register locations by the user. (initial=00H) 7 Mnemonic: DPS DPS.0: 6 5 4 3 2 Address: 86h 1 0 DPS.0
DATA POINTER SELECT Bit:
This bit is used to select the DPL, DPH pair or the DPL1, DPH1 pair as the active Data Pointer. When set to 1, DPL1, DPH1 will be selected, otherwise DPL, DPH will be selected.
DPS.1-7: These bits are reserved, but will read 0. POWER CONTROL Bit: 7 SMOD Mnemonic: PCON 6
SMOD0
(initial=00H) 5 SFS 4 IDLT 3 GF1 2 GF0 Address: 87h 1 PD 0 IDL
SMOD: This bit doubles the serial port0 baud rate in mode 1, 2, and 3 when set to 1. SMOD0: Framing Error Detection Enable: When SMOD0 is set to 1, and then SCON.7 indicates a Frame Error and acts as the FE flag. When SMOD0 is 0, then SCON.7 acts as SM0. SFS: Serial port0 mode1 and mode3 frequency source switch. SFS=0 SFS=1 IDLT: Serial port0 mode1 and mode3 frequency source is from Timer0 Serial port0 mode1 and mode3 frequency source is from Timer1
This bit controls the idle mode type. In idle mode when idle mode is released by any interrupt, if IDLT=1 it will not jump to the corresponding interrupt; if IDLT=0 it will jump to the corresponding interrupt. These two bits are general-purpose user flags. Setting this bit causes the W925EP01 to go into the POWER DOWN mode. In this mode all the clocks are stopped and program execution is frozen. Power down mode can be released by INT0~INT3 and ring detection of CID interrupt. Setting this bit causes the W925EP01 to go into the IDLE mode. The type of idle mode is selected by IDLT. In this mode the clocks to the CPU are stopped, so program execution is frozen. But the clock path to the timer blocks and interrupt blocks is not stopped, and these blocks continue operating. (initial=00H) Bit: 7 TF1 Mnemonic: TCON 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0
GF1-0: PD:
IDL:
TIMER CONTROL
Address: 88h
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W925EP01/ W925EP01FG
TF1: Timer 1 overflows flag. This bit is set when Timer 1 overflows. It is cleared automatically when the program does a timer 1 interrupt service routine. Software can also set or clear this bit. TR1: Timer 1 runs control. This bit is set or cleared by software to turn timer on or off. TF0: Timer 0 overflows flag. This bit is set when Timer 0 overflows. It is cleared automatically when the program does a timer 0 interrupt service routine. Software can also set or clear this bit. TR0: Timer 0 runs control. This bit is set or cleared by software to turn timer on or off. IE1: Interrupt 1 edge detects: Set by hardware when an edge/level is detected on INT1. This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. Otherwise, it follows the pin. Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered external inputs. Interrupt 0 edge detects: Set by hardware when an edge/level is detected on INT0 . This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. Otherwise, it follows the pin. Interrupt 0 type control. Set/cleared by software to specify falling edge/ low level triggered external inputs. (initial=00H) 7 GATE Mnemonic: TMOD Bit7~4 control timer 1, bit3~0 control timer0 GATE: Gating control. When this bit is set, Timer x is enabled only while INTx pin is high and TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set. C/ T : Timer or Counter Select. When cleared, the timer is incremented by internal clocks. When set, the timer counts high-to-low edges of the Tx pin. 6 C/ T 5 M1 4 M0 3 GATE 2 C/ T Address: 89h 1 M1 0 M0
IT1: IE0:
IT0:
TIMER MODE CONTROL Bit:
Note: X is either 0 or 1. M1, M0: Mode Select bits: M1 0 0 1 1 M0 0 1 0 1 Mode Mode 0: 13-bits timer Mode 1: 16-bits timer Mode 2: 8-bits with auto-reload from Thx Reserved (initial=00H) 7 TL0.7 Mnemonic: TL0 6 TL0.6 5 TL0.5 4 TL0.4 3 TL0.3 2 TL0.2 1 TL0.1 0 TL0.0
TIMER 0 LOW BYTE Bit:
Address: 8Ah Publication Release Date: Apr. 10, 2006 Revision A2
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W925EP01/ W925EP01FG
TL0.7-0: Timer 0 low byte register. TIMER 1 LOW BYTE Bit: 7 TL1.7 Mnemonic: TL1 TL1.7-0: Timer 1 low byte register. TIMER 0 HIGH BYTE Bit: 7 TH0.7 Mnemonic: TH0 TH0.7-0: Timer 0 high byte register. TIMER 1 HIGH BYTE Bit: 7 TH1.7 Mnemonic: TH1 TH1.7-0: Timer 1 high byte register. CLOCK CONTROL1 Bit: 7 WD1 Mnemonic: CKCON1 6 WD0 5 T1S1 4 T1S0 3 T0S1 (initial=00H) 2 T0S0 1 DIVS 0
M /S
(initial=00H) 6 TL1.6 5 TL1.5 4 TL1.4 3 TL1.3 2 TL1.2 1 TL1.1 0 TL1.0
Address: 8Bh
(initial=00H) 6 TH0.6 5 TH0.5 4 TH0.4 3 TH0.3 2 TH0.2 1 TH0.1 0 TH0.0
Address: 8Ch
(initial=00H) 6 TH1.6 5 TH1.5 4 TH1.4 3 TH1.3 2 TH1.2 1 TH1.1 0 TH1.0
Address: 8Dh
Address: 8Eh
WD1-0: Watchdog timer mode select bits: These bits determine the time-out period for the watchdog timer. In all four time-out options the reset time-out is 512 clocks more than the interrupt timeout period.
WD1 0 0 1 1
WD0 0 1 0 1
Interrupt time-out Fosc/2
12
Reset time-out Fosc/212 + 512 Fosc/215 + 512 Fosc/218 + 512 Fosc/221 + 512
Fosc/215 Fosc/218 Fosc/221
T0S0-1&T1S0-1: Timer0 & Timer1 clock source mode select bits. These bits determine the timer0 & timer1 clock source.
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W925EP01/ W925EP01FG
T0S1 (T1S1) 0 0 1 1 DIVS = 0: Fs/213 DIVS= 1: Fs/214
M /S:
T0S0 (T1S0) 0 1 0 1
Pre-scale clock source Fosc/22 Fosc/26 Fosc/210 Fs
DIVS: Divider clock source control bit 1:
System clock source control bit:
M /S = 0: Fosc = XIN1 (FM) M /S = 1: Fosc = XIN2 (Fs)
CLOCK CONTROL2 Bit: 7 6 5 KT1 4 KT0 3 -
(initial=00H) 2 Address: 8Fh 1 0 -
ENBUZ BUZSL Mnemonic: CKCON2
ENBUZ: When ENBUZ=1 the BUZ pin works as buzzer output, otherwise BUZ pin is in floating state. BUZSL: Buzzer output selection. When BUZSL=0 BUZ is the output of octave tone. When BUZZL=1, BUZ is the output of key tone. KT1-0: Key tone frequency sources from divider. When divider is enabled, KT1 and KT0 determine the key tone frequency.
KT1 KT0 KEY TONE FREQUENCY
0 0 1 1 PORT 1 Bit: 7
0 1 0 1
Low 512Hz 1024Hz 2048Hz (initial=FFH) 6 P1.6 5 P1.5 4 P1.4 3 P1.3 2 P1.2 1 P1.1 0 P1.0
P1.7 Mnemonic: P1
Address: 90h
P1.7-0: P1 can be selected as input or output mode by the P1IO register, at initial reset, P1IO is set to 1, so P1 is used as input mode. When P1IO is set to 0, the P1 is used as CMOS output mode. When P1EF are set and P1IO are set as input mode P1 can be used as external interrupt source. The functions are listed below.
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
P1.0 : INT2.0 P1.1 : INT2.1 P1.2 : INT2.2 P1.3 : INT2.3 P1.4 : INT3.0 P1.5 : INT3.1 P1.6 : INT3.2 P1.7 : INT3.3
External Interrupt 2 External Interrupt 2 External Interrupt 2 External Interrupt 2 External Interrupt 3 External Interrupt 3 External Interrupt 3 External Interrupt 3 (initial=00H) 6 5 4 COMPF 3 DIVF 2 CIDF 1 IE3 0 IE2
EXTERNAL INTERRUPT FLAG Bit: 7 Mnemonic: EXIF DIVF: Divider overflow flag. CIDF: CID interrupt flag. Set by hardware when at least one of CID flags is set. IE3: IE2:
Address: 91h
COMPF: Comparator flag. Set by hardware when RESC bit is from low to high.
External Interrupt 3 flag. Set by hardware when a falling edge is detected on INT3. External Interrupt 2 flag. Set by hardware when a falling edge is detected on INT2. (initial=00H) 7 Mnemonic: RPAGE 6 5 4 LT 3 2 Address: 92h 1 0 PG
ROM PAGE POINTER Bit:
LT: Determines the MOVC content reading is from ROM page0 or page1. LT = 0 indicates the MOVC reading data is from the ROM page0. LT = 1 indicates the MOVC reading data is from the ROM page1. PG: Determines the program ROM page of the executing ROM page. PG = 0 indicates the executing program is in page 0, from 00000H-0FFFFH PG = 1 indicates the executing program is in page 1, from 10000H-1FFFFH P1 PINS STATUS Bit: 7 6 5 4 3 (initial=00H) 2 1 0
P1.7SR P1.6SR P1.5SR P1.4SR P1.3SR P1.2SR P1.1SR P1.0SR Mnemonic: P1SR Address: 93h
P1SR: Set when a falling edge is detected on the corresponding P1 pin, clear by software.
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W925EP01/ W925EP01FG
P0 I/O PORT CONTROL Bit: 7 P0.7IO Mnemonic: P0IO P0IO: P0 pins I/O control. 1: input mode 0: output mode P1 I/O PORT CONTROL Bit: 7 P1.7IO Mnemonic: P1IO P1IO: P1 pins I/O control. 1: input mode 0: output mode P2 I/O PORT CONTROL Bit: 7 P2.7IO Mnemonic: P2IO P2IO: P2 pins I/O control. 1: input mode 0: output mode P3 I/O PORT CONTROL Bit: 7 P3.7IO Mnemonic: P3IO P3IO: P3 pins I/O control. 1: input mode 0: output mode 6 P3.6IO 5 P3.5IO 4 P3.4IO 3 P3.3IO (initial=FFH, input mode) 2 P3.2IO 1 P3.1IO 0 P3.0IO 6 P2.6IO 5 P2.5IO 4 P2.4IO 3 P2.3IO (initial=FFH, input mode) 2 P2.2IO 1 P2.1IO 0 P2.0IO 6 P1.6IO 5 P1.5IO 4 P1.4IO 3 P1.3IO (initial=FFH, input mode) 2 P1.2IO 1 P1.1IO 0 P1.0IO 6 P0.6IO 5 P0.5IO 4 P0.4IO 3 P0.3IO (initial=FFH, input mode) 2 P0.2IO 1 P0.1IO 0 P0.0IO
Address: 94h
Address: 95h
Address: 96h
Address: 97h
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
SERIAL PORT0 CONTROL Bit: 7 SM0/FE Mnemonic: SCON 6 SM1 5 SM2 4 REN 3 TB8 (initial=00H) 2 RB8 Address: 98h 1 TI 0 RI
SM0/FE: Serial port0, Mode 0 bit or Framing Error Flag: The SMOD0 bit in PCON SFR determines whether this bit acts as SM0 or as FE. The operation of SM0 is described below. When used as FE, this bit will be set to indicate an invalid stop bit. This bit must be manually cleared in software to clear the FE condition. SM1: Serial port0 Mode bit 1: SM0 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Description Synchronous Asynchronous Asynchronous Asynchronous Length 8 10 11 11 Baud rate 4/12 Tclk variable 16/32 Tclk variable
SM2: In mode 2 or 3, if SM2 is set to 1, then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 0 and 1, bit SM2 can able to be changed by software. In mode 1, if SM2 = 1, then RI will not be activated if a valid stop bit was not received. In mode 0, the SM2 bit controls the serial port0 clock. REN: Receive enable. When set to 1 serial reception is enabled, otherwise reception is disabled. TB8: This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software as desired. RB8: In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0 it has no function. TI: Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in all other modes during serial transmission. This bit must be cleared by software. RI: Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bits time in the other modes during serial reception. However the restrictions of SM2 apply to this bit. This bit can be cleared only by software.
SERIAL DATA BUFFER Bit: 7 6 5 4 3
(initial=XXH) Read Only 2 1 0
SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0 Mnemonic: SBUF Address: 99h
SBUF.7-0: Serial data on the serial port0 is read from or written to this location. It actually consists of two separate internal 8-bit registers. One is the receive register, and the other is the transmit buffer. Any read access gets data from the receive data buffer, while write access is to the transmit data buffer.
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W925EP01/ W925EP01FG
P1 PINS INTERRUPT EABLE Bit: 7 6 5 4 3 (initial=00H) 2 1 0
P1.7EF P1.6EF P1.5EF P1.4EF P1.3EF P1.2EF P1.1EF P1.0EF Mnemonic: P1EF P1EF: P1 pins interrupt function enabled/disabled register 0: disable 1: enable P1 PULL-HIGH CONTROL Bit: 7 P1.7H Mnemonic: P1H P1H: Port1 pins pull-high resistor enable/disable 1: enable 0: disable (initial=00H) 7 P2.7H Mnemonic: P2H P2H: Port2 pins pull-high resistor enable/disable 1: enable 0: disable P3 PULL-HIGH CONTROL Bit: 7 P3.7H Mnemonic: P3H P3H: Port3 pins pull-high resistor enable/disable 1: enable 0: disable PORT 2 (initial=FFH) Bit: 7 P2.7 Mnemonic: P2 6 P2.6 5 P2.5 4 P2.4 3 P2.3 2 P2.2 1 P2.1 0 P2.0 6 P3.6H 5 P3.5H 4 P3.4H 3 P3.3H (initial=00H) 2 P3.2H 1 P3.1H 0 P3.0H 6 P2.6H 5 P2.5H 4 P2.4H 3 P2.3H 2 P2.2H 1 P2.1H 0 P2.0H 6 P1.6H 5 P1.5H 4 P1.4H 3 P1.3H (initial=00H) 2 P1.2H 1 P1.1H 0 P1.0H Address: 9Bh
Address: 9Dh
P2 PULL-HIGH CONTROL Bit:
Address: 9Eh
Address: 9Fh
Address: A0h Publication Release Date: Apr. 10, 2006 Revision A2
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W925EP01/ W925EP01FG
P2.7-0: Port 2 is an I/O port with internal pull-high resistor. P2 can be selected as input or output mode by the P2IO register. At initial reset, P2 is used as input mode. When P2IO is set to 0, P2 is used as CMOS output mode. HIGH BYTE REGISTER Bit: 7 HB.7 Mnemonic: HB 6 HB.6 5 HB.5 4 HB.4 3 HB.3 (initial=00H) 2 HB.2 1 HB.1 0 HB.0
Address: A1h
This register contains the high byte address during execution of " MOVX @Ri, " instructions. P4 PULL-HIGH CONTROL Bit: 7 P4.7H Mnemonic: P4H P4H: Port4 pins pull-high resistor enable/disable 1: enable 0: disable P5 PULL-HIGH CONTROL Bit: 7 P5.7H Mnemonic: P5H P5H: Port5 pins pull-high resistor enable/disable 1: enable 0: disable PORT 7 Bit: 7 P7.7 Mnemonic: P7 6 P7.6 5 P7.5 4 P7.4 3 P7.3 2 P7.2 1 P7.1 (initial=FFH) 0 P7.0 6 P5.6H 5 P5.5H 4 P5.4H 3 P5.3H (initial=00H) 2 P5.2H 1 P5.1H 0 P5.0H 6 P4.6H 5 P4.5H 4 P4.4H 3 P4.3H (initial=00H) 2 P4.2H 1 P4.1H 0 P4.0H
Address: A2h
Address: A3h
Address: A4h
P7.7-0: Port 7 is an I/O port with internal pull-high resistor. P7 can be selected as input or output mode by the P7IO register, at initial reset, P7IO is set to 1, P7 is used as input mode. When P7IO is set to 0, P7 is used as CMOS output mode. The special function of P7 is as data bus of external program ROM or external data RAM. The program memory on the standard 8052 can only be addressed to 64KB long. W925EP01 can extend to two 64KB program ROM banks; there are on-chip APROM bank and external program ROM bank. When PG=1, the P7 pins can be treated as data bus of external program ROM. When PG=0, the P7 pins can be treated as normal I/O.
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W925EP01/ W925EP01FG
When "MOVC A, @A+DPTR" is executed to read the external ROM data or "MOVX dest, src" is executed to access the external data RAM, the P7 pins can be treated as data bus of external data storages. P7 inputs the data <7:0> of the external ROM. Or, P7 inputs/outputs the data <7:0> of the external data RAM. PORT 6 Bit: 7 P6.7 Mnemonic: P6 6 P6.6 5 P6.5 4 P6.4 3 P6.3 2 P6.2 1 P6.1 (initial=FFH) 0 P6.0
Address: A5h
P6.7-0: Port 6 is an I/O port with internal pull-high resistor. P6 can be selected as input or output mode by the P6IO register, at initial reset, P6IO is set to 1, P6 is used as input mode. When P6IO is set to 0, P6 is used as CMOS output mode. The special function of P6 is as address bus of external program ROM or external data RAM. The program memory on the standard 8052 can only be addressed to 64KB long. W925EP01 can extend to two 64KB program ROM banks; there are on-chip APROM bank and external program ROM bank. When PG=1, the P6 pins can be treated as address high bus of external program ROM. When PG=0, the P6 pins can be treated as normal I/O. When "MOVC A, @A+DPTR" is executed to read the external ROM data or "MOVX dest, src" is executed to access the external data RAM, the P6 pins can be treated as address high bus of external data storages. PORT 4 Bit: 7 P4.7 Mnemonic: P4 6 P4.6 5 P4.5 4 P4.4 3 P4.3 (initial=FFH) 2 P4.2 Address: A6h 1 P4.1 0 P4.0
P4.7-0: Port 4 is an I/O port with internal pull-high resistor. P4 can be selected as input or output mode by the P4IO register. At initial reset, P4IO is set to 1; P4 is used as input mode. When P4IO is set to 0, P4 is used as CMOS output mode. Special function of P4 is described below.
P4.7-5 P4.4 P4.3 P4.2 P4.1 P4.0
I/O VPOS I/O VNEG SDATA1 SCLK1
Normal I/O Positive input of the comparator Normal I/O Negative input of the comparator Serial port1 data I/O Serial port1 clock I/O with Smith trigger in input path
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
PORT 5 Bit: 7 P5.7 Mnemonic: P5 6 P5.6 5 P5.5 4 P5.4 3 P5.3 (initial=FFH) 2 P5.2 1 P5.1 0 P5.0
Address: A7h
P5.7-0: Port 5 is an I/O port with internal pull-high resistor. P5 can be selected as input or output mode by the P5IO register, at initial reset, P5IO is set to 1, P5 is used as input mode. When P5IO is set to 0, P5 is used as CMOS output mode. The special function of P5 is as address bus of external program ROM or external data RAM. The program memory on the standard 8052 can only be addressed to 64KB long. W925EP01 can extend to two 64KB program ROM banks, there are on-chip APROM bank and external program ROM bank. When PG=1, the P5 pins can be treated as address high bus of external program ROM. When PG=0, the P5 pins can be treated as normal I/O. When "MOVC A, @A+DPTR" is executed to read the external ROM data or "MOVX dest, src" is executed to access the external data RAM, the P5 pins can be treated as address high bus of external data storages. INTERRUPT ENABLE Bit: 7 EA Mnemonic: IE EA: ES1: ES0: Global enable. Enable/disable all interrupts. Enable Serial port1 interrupt Enable Serial port0 interrupt 6 ES1 5 4 ES0 3 ET1 (initial=00H) 2 EX1 1 ET0 0 EX0
Address: A8h
ET1: Enable Timer 1 interrupt EX1: Enable external interrupt 1 ET0: Enable Timer 0 interrupt EX0: Enable external interrupt 0
P6 PULL-HIGH CONTROL Bit: 7 P6.7H Mnemonic: P6H P6H: Port6 pins pull-high resistor enable/disable 1: enable 0: disable 6 P6.6H 5 P6.5H 4 P6.4H 3 P6.3H
(initial=00H) 2 P6.2H 1 P6.1H 0 P6.0H
Address: AAh
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W925EP01/ W925EP01FG
P7 PULL-HIGH CONTROL Bit: 7 P7.7H Mnemonic: P7H P7H: Port7 pins pull-high resistor enable/disable 1: enable 0: disable P7 I/O PORT CONTROL Bit: 7 P7.7IO Mnemonic: P7IO P7IO: P7 pins I/O control. 1: input mode 0: output mode P6 I/O PORT CONTROL Bit: 7 P6.7IO Mnemonic: P6IO P6IO: P6 pins I/O control. 1: input mode 0: output mode 6 P6.6IO 5 P6.5IO 4 P6.4IO 3 P6.3IO (initial=FFH, input mode) 2 P6.2IO 1 P6.1IO 0 P6.0IO 6 P7.6IO 5 P7.5IO 4 P7.4IO 3 P7.3IO (initial=FFH, input mode) 2 P7.2IO 1 P7.1IO 0 P7.0IO 6 P7.6H 5 P7.5H 4 P7.4H 3 P7.3H (initial=00H) 2 P7.2H 1 P7.1H 0 P7.0H
Address: ABh
Address: ACh
Address: ADh
P4 I/O PORT CONTROL Bit: 7 P4.7IO Mnemonic: P4IO P4IO: P4 pins I/O control. 1: input mode 0: output mode 6 P4.6IO 5 P4.5IO 4 P4.4IO 3 P4.3IO
(initial=FFH, input mode) 2 P4.2IO 1 P4.1IO 0 P4.0IO
Address: AEh
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
P5 I/O PORT CONTROL Bit: 7 P5.7IO Mnemonic: P5IO P5IO: P5 pins I/O control. 1: input mode 0: output mode PORT 3 Bit: 7 P3.7 Mnemonic: P3 6 P3.6 5 P3.5 4 P3.4 3 P3.3 2 P3.2 (initial=FFH) 1 P3.1 0 P3.0 6 P5.6IO 5 P5.5IO 4 P5.4IO 3 P5.3IO (initial=FFH, input mode) 2 P5.2IO 1 P5.1IO 0 P5.0IO
Address: AFh
Address: B0h
P3.7-0: P3 can be selected as input or output mode by the P3IO register, at initial reset, P3IO is set to 1, P3 is used as input mode. When P3IO is set to 0, the P3 is used as CMOS output mode. Special function of P3 is described below. P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 CID REGISTER Bit: 7 Mnemonic: CIDR FCLK: FSK serial clock with the baud rate of 1200Hz. FDATA: FSK serial bit data. FCD: Set when FSK carrier is detected. Cleared when FSK carrier is disappeared. DTMFD: Set when DTMF decoded data is ready. Cleared when DTMF signal ends. FDR: Set when FSK 8 bits data is ready. Cleared before next FSK start bit comes ALGO: Dual tone Alert signal Guard time detect signal. Set when a guard time qualified dual tone alert signal has been detected. Cleared when the guard time qualified dual tone alert signal is absent. - 28 6 FCLK 5 FDATA 4 FCD
RD
WR
Read low pulse signal when reading external RAM Write low pulse signal when writing external RAM Timer/counter 1 external count input Timer/counter 0 external count input External interrupt 1 External interrupt 0 Serial port0 output Serial port0 input (initial=00H, read only) 3 DTMFD 2 FDR Address: B1h 1 ALGO 0 RNG
T1 T0
INT1
INT0
TxD RxD
This SFR indicates the CID signal immediately. Register data is set or cleared by hardware only.
W925EP01/ W925EP01FG
RNG: Ring detection bit. High will be indicated the detection of line reversal and/or ringing. CID FLAG GENERATOR Bit: 7 Mnemonic: CIDFG FSF: Set when FSK Latch clock low to high. Cleared by software DTMFDF: Set when DTMFD low to high. Cleared by software FDRF: Set when FDR low to high. Cleared by software. ALGOF: Set when ALGO low to high. Cleared by software. RNGF: Set when RNG low to high. Cleared by software. CID POWER CONTROL REGISTER Bit: 7 Mnemonic: CIDPCR FSKE: Enable FSK demodulation circuit. CASE: Enable Dual Tone Alert Signal detection circuit. DTMFE: Enable DTMF demodulation circuit. FSK DATA REGISTER Bit: 7 FD7 Mnemonic: FSKDR FD7-0: 8 bits FSK demodulated data. (initial=XXH) 7 CASH CASH: CASL: 6 CASL 5 4 3 DD3 2 DD2 Address: B5h 1 DD1 0 DD0 6 FD6 5 FD5 4 FD4 3 FD3 (initial=XXH) 2 FD2 Address: B4h 1 FD1 0 FD0 6 5 4 CIDE 3 (initial=00H) 2 FSKE Address: B3h 1 CASE 0 DTMFE 6 5 4 FSF 3 (initial=00H) 2 Address: B2h 1 ALGOF 0 RNGF
DTMFDF FDRF
CIDE: Global enable CID function. Low to disable all functions of CID parts.
DTMF DATA REGISTER Bit:
DTMFH DTMFL
Mnemonic: DTMFDR Set when Dual Tone Alert Signal high tone is detected. Set when Dual Tone Alert Signal low tone is detected.
DTMFH: Set when DTMF high tone is detected. DTMFL: Set when DTMF low tone is detected. DD3-0: 4 bits DTMF demodulated data.
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
DTMF PRESENT TIME REGISTER Bit: 7 DPT7 Mnemonic: DTMFPT 6 DPT6 5 DPT5 4 DPT4 3 DPT3 (initial=19H) 2 DPT2 Address: B6h 1 DPT1 0 DPT0
The clock period of guard-time timer is 0.8582mS. The default DTMF present time is 21.45mS. DPT7-0: The pre-set data register for counting DTMF present time. When DTMF is detected (ESt, low to high), the guard timer starts to up-count from 00H. As the guard timer is equal to the value of DTMFPT, while exist of the DTMF is accepted. ESt changes to low state to stop and reset the counter. DTMF ABSENT TIME REGISTER Bit: 7 DAT7 Mnemonic: DTMFAT 6 DAT6 5 DAT5 4 DAT4 3 DAT3 (initial=19H) 2 DAT2 Address: B7h 1 DAT1 0 DAT0
The clock period of guard-time timer is 0.8582mS. The default DTMF absent time is 21.45mS. DAT7-0: The pre-set data register for counting DTMF absent time. When DTMF is absent (ESt, high to low), the guard timer starts to up-count from 00H. As the guard timer is equal to the value of DTMFAT, the finish of DTMF is recognized. ESt changes to low state to stop and reset the counter. INTERRUPT PRIORITY Bit: 7 6 PS1 5 4 PS0 (initial=00H) 3 PT1 2 PX1 1 PT0 0 PX0
Mnemonic: IP IP.7: This bit is un-implemented and will read high. PS1: PS0:
Address: B8h
This bit defines the Serial port1 interrupt priority. PS1 = 1 sets it to higher priority level. This bit defines the Serial port0 interrupt priority. PS0 = 1 sets it to higher priority level.
PT1: This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level. PX1: This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level. PT0: This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level. PX0: This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level. DTMF AND CAS GENERATOR REGISTER Bit: 7 CASGE 6 DTGE 5 HE 4 LE 3 L1 (initial=00H) 2 L0 1 H1 Address: BAh 0 H0
Mnemonic: DTMFG CASGE: Enable CAS tone output to DTMF pin. DTGE: Enable dual tone output to DTMF pin. - 30 -
W925EP01/ W925EP01FG
HE: Enable CAS/DTMF high group frequency output. LE: Enable CAS/DTMF low group frequency output.
CAS SELECTED TONE
L1
L0
H1
H0
SELECTED TONE
HE
LE
x x x x 0 0 1 1
X X X X 0 1 0 1
0 0 1 1 x x x x
0 1 0 1 X X X X
1209Hz 1336Hz 1477Hz 1633Hz 697Hz 770Hz 852Hz 941Hz
0 0 1 1
0 1 0 1
Low 2130Hz 2750Hz 2130Hz & 2750Hz
COMPARATOR REGISTER Bit: 7 6 5 4 3 RESC 2 -
(initial=00H) 1 0 COMPEN
Mnemonic: COMPR RESC:
Address: BBh
Result of the comparator. Set when positive analog input voltage is (VPOS) higher than negative analog input voltage (VNEG) RESC is a read only bit. COMPEN=0 Disable comparator COMPEN=1 Enable comparator
COMPEN:
IDLE RELEASED CONDITION REGISTER 1 Bit: 7 Mnemonic: IRC1 6 IRCS1 5 4 IRCS1 3 IRCT1
(initial=00H) 2 IRCX1 1 IRCT0 0 IRCX0
Address: BCh
One of the bits of IRC1 and IRC2 will be set by hardware to record the idle released condition when the idle mode is released. IRC1 and IRC2 can be set by hardware and can be R/W by software. IRCS1: Idle mode released by Serial port1 interrupt flag. IRCS0: Idle mode released by Serial port0 interrupt flag. IRCT1: Idle mode released by Timer1 interrupt flag. IRCX1: Idle mode released by external interrupt 1 flag. IRCT0: Idle mode released by Timer0 interrupt flag.
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
IRCX0: Idle mode released by external interrupt 0 flag. IDLE RELEASED CONDITION REGISTER 2 Bit: 7 Mnemonic: IRC2 6 5 4 3 (initial=00H) 2 1 IRCX3 0 IRCX2
IRCWDI IRCCOMP IRCDIV IRCCID
Address: BDh
One of the bits of IRC1 and IRC2 will be set by hardware to record the idle released condition when the idle mode is released. IRC1 and IRC2 can be set by hardware and can be R/W by software. IRCWDI: Idle mode released by Watchdog timer interrupt flag. IRCCOMP: Idle mode released by comparator interrupt flag. IRCDIV: Idle mode released by Divider interrupt flag. IRCCID: Idle mode released by CID interrupt flag. IRCX3: Idle mode released by External Interrupt 3 flag. IRCX2: Idle mode released by External Interrupt 2 flag. CAS TONE PRESENT TIME REGISTER Bit: 7 6 5 4 3 (initial=0FH) 2 Address: BEh 1 0
CASPT7 CASPT6 CASPT5 CASPT4 CASPT3 CASPT2 CASPT1 CASPT0 Mnemonic: CASPT The clock period of guard-time timer is 0.8582mS. The initial alert tone present time is 12.87mS. CASPT7-0: The pre-set data register for counting CAS tone present time. When CAS tone is detected (ALGR: low to high), the guard timer starts to up-count from 00H. As the guard timer is equal to the value of CASPT, the existence of the CAS tone is accepted. ALGR changes to low state to stop and reset the counter. CAS TONE ABSENT TIME REGISTER Bit: 7 6 5 4 (initial=0FH) 3 2 Address: BFh 1 0
CASAT7 CASAT6 CASAT5 CASAT4 CASAT3 CASAT2 CASAT1 CASAT0 Mnemonic: CASAT The clock period of guard-time timer is 0.8582mS. The initial alert tone absent time is 12.87mS. CASAT7-0: The pre-set data register for counting CAS tone absent time. When CAS tone is absent (ALGR: high to low), the guard timer starts to up-count from 00H. As the guard timer is equal to the value of CASAT, the finish of CAS tone is recognized. ALGR changes to high state to stop and reset the counter. SERIAL PORT CONTROL 1 Bit: 7 SF1 6 5 REGON 4 REN1 3 SFQ (initial=00H) 2 SEDG 1 CLKIO 0 SIO
Mnemonic: SCON1
Address: C0h
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W925EP01/ W925EP01FG
SF1: Serial port1 interrupt flag. When 8-bits data transited completely, SF1 is set by hardware. SF1 is cleared when serial interrupt routine is executed or cleared by software. Set REN1 from 0 to 1 to start the serial port to receive 8-bit serial data. SFQ=0 Serial clock output frequency is equal to Fosc /2 SFQ=1 Serial clock output frequency is equal to Fosc /256 SEDG: SEDG=0 Serial data latched at falling edge of clock, SCLK=Low initially. SEDG=1 Serial data latched at rising edge of clock, SCLK=High initially CLKIO: CLKIO=0 P4.0 (SCLK) work as output mode CLKIO=1 P4.0 (SCLK) work as input mode SIO: SIO=0 P4.0 & P4.1 work as normal I/O pin SIO=1 P4.0 & P4.1 work as Serial port1 function SERIAL DATA BUFFER 1 Bit: 7 6 5 4 3 (initial=00H) Read Only 2 1 0
REGON: Regulator on/off control. 0 will disable regulator, 1 will enable regulator. REN1: SFQ:
SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0 Mnemonic: SBUF1 Address: C1h
SBUF1.7-0: Serial data on the serial port1 is read from or written to this location. It actually consists of two separate internal 8-bit registers. One is the receive register, and the other is the transmit buffer. Any read access gets data from the receive data buffer, while write access is to the transmit data buffer. POWER MANAGEMENT REGISTER Bit: 7 XT/ RG 6 RGMD 5 RGSL 4 X2OFF 3 X1OFF (initial=10000XX1B) 2
-
1 -
0 DME0
Mnemonic: PMR
Address: C4h
XT/ RG : Crystal/RC Oscillator Select. Setting this bit selects crystal or external clock as system clock source. Clearing this bit selects the on-chip RC oscillator as clock source. X1UP (STATUS.4) must be set to 1 and X1OFF (PMR.3) must be cleared before this bit can be set. Attempts to set this bit without obeying these conditions will be ignored. RGMD: RC Mode Status. This bit indicates the current clock source of micro-controller. When it is cleared, CPU is operating from the external crystal or oscillator. When it is set, CPU is operating from the on-chip RC oscillator. RGSL: RC Oscillator Select. This bit selects the clock source following a resume from Power Down Mode. Setting this bit allows device operating from RC oscillator when a resume from Power down Mode. When this bit is cleared, the device will hold operation until the crystal oscillator has warmed-up following a resume from Power down Mode. X2OFF: Set to disable sub-oscillator (32 KHz oscillator) X1OFF: Crystal Oscillator Disable. Setting this bit disables the external crystal oscillator. This bit can only be set to 1 while the micro-controller is operating from the RC oscillator. Clearing this bit Publication Release Date: Apr. 10, 2006 Revision A2
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W925EP01/ W925EP01FG
restarts the crystal oscillator, the X1UP (STATUS.4) bit will be set after crystal oscillator warmed-up has completed. DME0: This bit determines the on-chip MOVX SRAM to be enabled or disabled. Set this bit to 1(default) will enable the on-chip 4K bytes MOVX SRAM. Clear this bit to 0 will disable the onchip 4K bytes MOVX SRAM. The W925EP01 contains on-chip 4K MOVX SRAM of Data Memory, which can only be accessed by MOVX instructions from the address 000H to FFFH. Access to the on-chip MOVX SRAM is optional by software setting DME0, MOVX addresses greater than FFFH automatically go to external memory through A0 to A15; this is the default condition. When DME0 be clearing, the 4K data memory area is transparent to the system memory map. Any MOVX directed to the space between 0000H to FFFFH goes to expanded bus on A0 to A15. STATUS REGISTER Bit: 7 X2UP 6 HIP 5 LIP 4 X1UP 3 (initial=00H) 2
-
1 -
0 -
Mnemonic: STATUS
Address: C5h
X2UP: Sub-crystal oscillator warm-up status. When set, this bit indicates the crystal oscillator has completed the warm-up delay. When X2OFF bit is set, hardware will clear this bit. There are two options which are selected by option code for warm-up delay, one is 1024 clocks warm-up delay, and other is 65536 clocks warm-up delay. HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority interrupt. This bit will be cleared when the program executes the corresponding RETI instruction. LIP: Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority interrupt. This bit will be cleared when the program executes the corresponding RETI instruction. X1UP: Crystal Oscillator Warm-up Status. When set, this bit indicates the crystal oscillator has completed the 65536 clocks warm-up delay. Each time the crystal oscillator is restarted by exit from power down mode or the X1OFF bit is set, hardware will clear this bit. This bit is set to 1 after a power-on reset. When this bit is cleared, it prevents software from setting the XT/ RG bit to enable CPU operation from crystal oscillator. There are two options which are selected by option code for warm-up delay, one is 4096 clocks warm-up delay, and other is 65536 clocks warm-up delay. FSK TRANSIMT CONTROL REGISTER Bit: 7 FTE Mnemonic: FSKTC FTE: FSK transmit Enable; Enable=1, Disable=0 FTM: FSK signal Standard; Bellcore=1, V.23=0 FDS: FSK data sending status LO0, LO1: CAS/FSK transmitting level option. levels of 2750Hz will higher 2dBm than it. In CAS tone, it just is suitable for 2130Hz. The output 6 FTM 5 FDS 4 3 2 (initial=00H) 1 LO1 0 LO0
Address: C6h
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W925EP01/ W925EP01FG
FSK output level 150mV 125mV 100mV 75mV
LO1 0 0 1 1
LO0 0 1 0 1
FSK TRANSMIT DATA BUFFER Bit: 7 Mnemonic: FSKTB FSKTB.0: Only this bit will be latched and send out as FSK signal DIVIDER CONTROL Bit: 7 Mnemonic: DIVC 6 5 4 3 6 5 4 3 -
(initial=00H) 2 Address: C7h 1 0 FSKTB.0
(initial = 01H) 2 Address: C8h 1 0 DIVA
DIVA: Divider available control bit. This bit is set or cleared by software to enable/disable divider. DIVA = 1 to enable the divider. DIVA = 0 to disable the divider. DIVA is reset after reset. BAUD RATE GENERATOR CONTROL REGISTER Bit: 7 Mnemonic: BGCON 6 5 4 3 (initial=00000110B) 2 1 0 BGEN
RCKEN TCKEN Address: CEh
BGEN: BG-Counter control bit. Enable/Disable baud rate generator counter. 0: Disable; 1: Enable. TCKEN: Select the transmission clock source of serial port0. When TCKEN=1, the clock source come from the BG-counter; otherwise, the clock source come from Timer0 or Timer1. RCKEN: Select the receiving clock source of serial port0. When RCKEN=1, the clock source come from the BG-counter; otherwise, the clock source come from Timer0 or Timer1. BAUD RATE GENERATOR RELOAD REGISTER rate of serial port0) Bit: 7 BG.7 Mnemonic: BG 6 BG.6 5 BG.5 4 BG.4 3 BG.3 (initial=1AH for 9600 baud 2 BG.2 1 BG.1 0 BG.0
Address: CFh
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
BG: Move the proper value into this register for generating the baud rate of serial port0. When BGCounter is overflow, the content of BG will be reloaded into the BG-Counter. The baud rate of serial port0 is generated by Fm/BG/16. Example: if Fm=4MHz and the content of BG is 1Ah (initial value), the baud rate = 4000000/26/16 = 9615Hz; if the content of BG is changed to 0Dh, the baud rate should be 4000000/13/16 = 19230Hz. PROGRAM STATUS WORD Bit: 7 CY CY: AC: F0: 6 AC 5 F0 4 RS1 3 RS0 (initial=00H) 2 OV 1 F1 0 P
Mnemonic: PSW Address: D0h Carry flag. Set for an arithmetic operation, which results in a carry being generated from the ALU. It is also used as the accumulator for the bit operations. Auxiliary carry. Set when the previous operation resulted in a carry from the high order nibble. User flag 0: General purpose flag. That can be set or cleared by the user.
RS1 RS0 REGISTER BANK ADDRESS
RS.1-0: Register bank selection bits: 0 0 1 1 OV: F1: P: 0 1 0 1 0 1 2 3 00-07h 08-0Fh 10-17h 18-1Fh
Overflow flag. Set when a carry was generated from the seventh bit but not from the 8th bit as a result of the previous operation, or vice-versa. User Flag 1: General purpose flag. That can be set or cleared by the user by software. Parity flag. Set/cleared by hardware to indicate odd/even number of 1's in the accumulator. (initial: note) 7 6 POR 5 4 WFS 3 WDIF 2 WTRF 1 EWT 0 RWT
WATCHDOG CONTROL Bit:
Mnemonic: WDCON Address: D8h POR: Power-on reset flag. Hardware will set this flag when system is powered on and this flag is cleared only by software. WFS: Watchdog Timer Frequency Select. Set to select FS as WDT clock input. Clear to select FOSC as WDT clock input. WDIF: Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the watchdog timer. If the Watchdog interrupt is enabled (EIE.5), then an interrupt will occur (if the global interrupt enable is set and other interrupt requirements are met). Software or any reset can clear this bit.
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W925EP01/ W925EP01FG
WTRF: Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a reset. Software can read it but must clear it manually. A power-fail reset will also clear the bit. This bit helps software in determining the cause of a reset. If EWT = 0, the watchdog timer will have no effect on this bit. EWT: Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer Reset function. RWT: Reset Watchdog Timer. This bit helps in putting the watchdog timer into a known state. It also helps in resetting the watchdog timer before a time-out occurs. Failing to set the EWT before time-out will cause an interrupt, if EWDI (EIE.5) is set, and 512 clocks after that a watchdog timer reset will be generated if EWT is set. This bit is self-clearing by hardware. Note: The WDCON SFR is set to a 0x000xx0b on an external reset. WTRF is set to a 1 on a Watchdog timer reset, but to a 0 on power on/down resets. WTRF is not altered by an external reset. POR is set to 1 by a power-on reset. EWT is set to 0 on a Power-on reset and unaffected by other resets. ACCUMULATOR Bit: 7 ACC.7 Mnemonic: ACC ACC.7-0: The ACC register.
ISP ADDRESS LOW BYTE (INITIAL=00H)
(initial=00H) 6 ACC.6 5 ACC.5 4 ACC.4 3 ACC.3 2 ACC.2 1 ACC.1 0 ACC.0
Address: E0h
Bit:
7 A7
6 A6
5 A5
4 A4
3 A3
2 A2
1 A1
0 A0
Mnemonic: SFRAL
Address: E4h
The low byte destination address is for In System Programming operations. The SFRAH and SFRAL address register are specific ROM bytes for erasure, programming or read.
ISP ADDRESS HIGH BYTE (INITIAL=00H)
Bit:
7 A15
6 A14
5 A13
4 A12
3 A11
2 A10
1 A9
0 A8
Mnemonic: SFRAH
Address: E5h
The high byte destination address is for In System Programming operations. The SFRAH and SFRAL address are specific ROM bytes for erasure, programming or read.
ISP DATA BUFFER (INITIAL=FFH)
Bit:
7 D7
6 D6
5 D5
4 D4
3 D3
2 D2
1 D1
0 D0
Mnemonic: SFRFD
Address: E6h
In ISP mode, read/write a specific byte ROM content must go through SFRFD register.
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
ISP OPERATION MODES (INITIAL=3FH)
Bit:
7 -
6
5
4 CEN
3 CTRL3
2 CTRL2
1 CTRL1
0 CTRL0
WFWIN OEN Mnemonic: SFRCN
Address: E7h
WFWIN: Destination ROM bank for programming, erasure and read. 0 = AP FLASH EPROM, 1 = LD FLASH EPROM. OEN: Flash EPROM output enable. CEN: Flash EPROM chip enable. CTRL [3:0]: Mode Selection.
SFRAH, SFRAL
MODE
WFWIN
OEN
CEN
CTRL<3:0>
SFRFD
Erase 64KB APROM Program 64KB APROM Read 64KB APROM Erase 4KB LDROM Program 4KB LDROM Read 4KB LDROM
0 0 0 1 1 1
1 1 0 1 1 0
0 0 0 0 0 0
0010 0001 0000 0010 0001 0000
X Address in Address in X Address in Address in (initial=00H)
X Data in Data out X Data in Data out
EXTENDED INTERRUPT ENABLE Bit: 7 6 5 EWDI 4 ECOMP 3 EDIV
2 ECID
1 EX3 Address: E8h
0 EX2
Mnemonic: EIE EIE.7-6: Reserved bits. EWDI: Enable Watchdog timer interrupt. ECOMP: Enable comparator interrupt. EDIV: Enable Divider interrupt. ECID: Enable CID interrupt. EX3: External Interrupt 3 Enable. EX2: External Interrupt 2 Enable.
TIMED ACCESS
(INITIAL=FFH)
Bit:
7 TA.7
6 TA.6
5 TA.5
4 TA.4
3 TA.3
2 TA.2
1 TA.1 Address: EEh
0 TA.0
Mnemonic: TA
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W925EP01/ W925EP01FG
TA: The Timed Access register controls the access to protected bits. To access protected bits, the user must first write AAH to the TA. This must be immediately followed by a write of 55H to TA. Now a window is opened in the protected bits for three machine cycles, during which the user can write to these bits.
IN-SYSTEM PROGRAMMING CONTROL REGISTER (INITIAL=00H)
Bit:
7
SWRHWB
6
-
5
LDAP
4
-
3
-
2
-
1
FBOOTSL
0
FPROGEN
Mnemonic: CHPCON
BIT NAME FUNCTION
Address: EFh
7
SWRHWB Set this bit to launch a whole device reset that is same as asserting high to RESET pin, micro-controller will be back to initial state and clear this bit automatically. To read this bit, its alternate function to indicate the ISP hardware reboot mode is invoking when read it in high. LDAP Reserve. This bit is Read Only. High: device is executing the program in LD Flash EPROM. Low: device is executing the program in AP Flash EPROM. Reserve. Reserve. Reserve.
6 5
4 3 2 1 0
-
FBOOTSL Loader program residence selection. Set to high to route the device fetching code from LDROM. FPROGEN In System Programming Mode Enable. Set this bit to launch the ISP mode. Device will operate ISP procedures, such as Erase, Program and Read operations, according to correlative SFRs settings. During ISP mode, device achieves ISP operations by the way of IDLE state. In the other words, device is not indeed in IDLE mode is set bit PCON.1 while ISP is enabled. Clear this bit to disable ISP mode, device get back to normal operation including IDLE state. (initial=00H) Bit: 7 B.7 Mnemonic: B 6 B.6 5 B.5 4 B.4 3 B.3 2 B.2 1 B.1 0 B.0
B REGISTER
Address: F0h
B.7-0: The B register serves as a second accumulator.
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
EXTENDED INTERRUPT PRIORITY Bit: 7 Mnemonic: EIP PCOMP: Comparator interrupt priority. 0 = Low priority, 1 = High priority. PDIV: Divider Interrupt Priority. 0 = Low priority, 1 = High priority. PCID: CID Interrupt Priority. 0 = Low priority, 1 = High priority. PX3: PX2: External Interrupt 3 Priority. 0 = Low priority, 1 = High priority. External Interrupt 2 Priority. 0 = Low priority, 1 = High priority. (initial=00H) 7 BIT7 Mnemonic: CIDGD 6 BIT6 5 BIT5 4 BIT4 3 BIT3 2 BIT2 1 BIT1 0 BIT0 6 5 PWDI 4 PCOMP 3 PDIV (initial=00H) 2 PCID 1 PX3 0 PX2
Address: F8h
PWDI: Watchdog timer interrupt priority. 0 = Low priority, 1 = High priority.
CID GAIN CONTROL DATA Bit:
Address: F9h
CIDGD.7-0: The data value of programmable CID input filter gain and hysteresis. CID GAIN CONTROL ADDRESS Bit: 7 Mnemonic: CIDGA CIDGA.3: 6 5 4 3 BIT3 (initial=00H) 2 BIT2 1 BIT1 0 BIT0
Address: FAh
The CIDGD latch control signal. The rising high pulse latch CIDGD into CID gain control register.
CIDGA.2-0: The address to indicate CID input gain control registers.
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W925EP01/ W925EP01FG
6.3 Initial State of Registers
RESET INITIAL VALUE
The following table lists the initial state of registers after different reset functions.
SFR ITEM POR WDT RESET
SDRAL, SFRAH, CHPCON SFRFD, TA SFRCN ACC, B, STATUS, PSW SP RPAGE P0, P1, P2, P3, P4, P0IO, P1IO, P2IO, P3IO, P4IO P5, P6, P7, P5IO, P6IO, P7IO DPL, DPH, DPL1, DPH1, DPS PCON, TCON, TMOD TL0, TL1, TH0, TH1 CKCON1, REGVC SBUF EIF, IE, HB, IP, EIE, EIP P1SR, P1EF, P1H, P2H, P3H, P4H, P5H, P6H, P7H CIDR, CIDFG, CIDPCR, CIDGD, CIDGA FSKDR, DTMFDR DTMFPT, DTMFAT DTMFG, COMPR, IRC1, IRC2, FSKTC, FSKTB CASPT, CASAT PMR BG BGCON WDCON x: Un-used u: unchanged *: Depend on circuit detection CKCON2, SCON, SCON1, SBUF1,
00h ffh 3Fh 00h 07h 00h ffh 00h 00h 00h 00h ******** B 00h 00h 00h ******** B 19h 00h 0fh 10000xx1B 1ah 06h 0u000uu0B
00h ffh 3Fh 00h 07h 00h ffh 00h 00h 00h 00h ******** B 00h 00h 00h ******** B 19h 00h 0fh 10000xx1B 1ah 06h 01000000B
00h ffh 3Fh 00h 07h 00h ffh 00h 00h 00h 00h ******** B 00h 00h 00h ******** B 19h 00h 0fh uuu00xx1B 1ah 06h 0u0001u0B
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
6.4 Instruction
The W925EP01 executes all the instructions of the standard 8032 family. However, timing of these instructions is different. In the W925EP01, each machine cycle consists of 4 clock periods, while in the standard 8032 it consists of 12 clock periods. Also, in the W925EP01 there is only one fetch per machine cycle i.e. 4 clocks per fetch, while in the standard 8032 there can be two fetches per machine cycle, which works out to 6 clocks per fetch. Table 2 Instructions that affect Flag settings
INSTRUCTION CARRY OVERFLOW AUXILIARY CARRY INSTRUCTION CARRY OVERFLOW AUXILIARY CARRY
INC, DEC ADD ADDC SUBB MUL DIV DA A RRC A RLC A
X X X 0 0 X X X
X X X X X
X X X
SETB C CLR C CPL C ANL C, bit ANL C, bit ORL C, bit ORL C, bit MOV C, bit CJNE
1 0 X X X X X X X
A "X" indicates that the modification is as per the result of instruction. A "-" indicates that the flag is not effected by the instruction. Table 3 Instruction Timing for W925EP01
Instruction NOP ADD A, R0 ADD A, R1 ADD A, R2 ADD A, R3 ADD A, R4 ADD A, R5 ADD A, R6 ADD A, R7 ADD A, @R0 ADD A, @R1 ADD A, direct ADD A, #data ADDC A, R0 ADDC A, R1 ADDC A, R2 ADDC A, R3 ADDC A, R4 ADDC A, R5 ADDC A, R6 ADDC A, R7 HEX Op-Code 00 28 29 2A 2B 2C 2D 2E 2F 26 27 25 24 38 39 3A 3B 3C 3D 3E 3F Bytes 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 Machine Cycles 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 Instruction ANL A, R0 ANL A, R1 ANL A, R2 ANL A, R3 ANL A, R4 ANL A, R5 ANL A, R6 ANL A, R7 ANL A, @R0 ANL A, @R1 ANL A, direct ANL A, #data ANL direct, A ANL direct, #data ANL C, bit ANL C, /bit CJNE A, direct, rel CJNE A, #data, rel CJNE @R0, #data, rel CJNE @R1, #data, rel CJNE R0, #data, rel HEX Op-Code 58 59 5A 5B 5C 5D 5E 5F 56 57 55 54 52 53 82 B0 B5 B4 B6 B7 B8 Bytes 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 3 3 3 3 3 Machine Cycles 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 4 4 4 4 4
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W925EP01/ W925EP01FG
Table 4 Instruction Timing for W925EP01, continued
Instruction ADDC A, @R0 ADDC A, @R1 ADDC A, direct ADDC A, #data
HEX Op-Code
Bytes 1 1 2 2 2 2 3 1 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 2 2 2 2 2 2 2 3 1 1 1 1
Machine Cycles 1 1 2 2 3 3 4 1 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 2 2 5 1 3 3 3 3 3 3 3 3 4 1 1 1 1
Instruction CJNE R1, #data, rel CJNE R2, #data, rel CJNE R3, #data, rel CJNE R4, #data, rel CJNE R5, #data, rel CJNE R6, #data, rel JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel LCALL addr16 LJMP addr16 MUL AB MOV A, R0 MOV A, R1 MOV A, R2 MOV A, R3 MOV A, R4 MOV A, R5 MOV A, R6 MOV A, R7 MOV A, @R0 MOV A, @R1 MOV A, direct MOV A, #data MOV R0, A MOV R1, A MOV R2, A MOV R3, A MOV R4, A MOV R5, A MOV R6, A MOV R7, A MOV R0, direct MOV R1, direct MOV R2, direct MOV R3, direct MOV R4, direct MOV R5, direct MOV R6, direct
HEX Op-Code B9 BA BB BC BD BE 40 50 20 30 10 12 02 A4 E8 E9 EA EB EC ED EE EF E6 E7 E5 74 F8 F9 FA FB FC FD FE FF A8 A9 AA AB AC AD AE
Bytes 3 3 3 3 3 3 2 2 3 3 3 3 3 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2
Machine Cycles 4 4 4 4 4 4 3 3 4 4 4 4 4 5 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2
36 37 35 34 71,91,B1,11,31, ACALL addr11 51,D1,F1 01,21,41,61,81, AJMP ADDR11 A1,C1,E1 CJNE R7, #data, rel BF CLR A E4 CPL A F4 CLR C C3 CLR bit C2 CPL C B3 CPL bit B2 DEC A 14 DEC R0 18 DEC R1 19 DEC R2 1A DEC R3 1B DEC R4 1C DEC R5 1D DEC R6 1E DEC R7 1F DEC @R0 16 DEC @R1 17 DEC direct 15 DEC DPTR A5 DIV AB 84 DA A D4 DJNZ R0, rel D8 DJNZ R1, rel D9 DJNZ R5, rel DD DJNZ R2, rel DA DJNZ R3, rel DB DJNZ R4, rel DC DJNZ R6, rel DE DJNZ R7, rel DF DJNZ direct, rel D5 INC A 04 INC R0 08 INC R1 09 INC R2 0A
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
Table 5 Instruction Timing for W925EP01, continued
Instruction INC R3 INC R4 INC R5 INC R6 INC R7 INC @R0 INC @R1 INC direct INC DPTR JMP @A+DPTR JZ rel JNZ rel MOV @R1, direct MOV @R0, #data MOV @R1, #data MOV direct, A MOV direct, R0 MOV direct, R1 MOV direct, R2 MOV direct, R3 MOV direct, R4 MOV direct, R5 MOV direct, R6 MOV direct, R7 MOV direct, @R0 MOV direct, @R1 MOV direct, direct MOV direct, #data MOV DPTR, #data 16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @R0 MOVX A, @R1 MOVX A, @DPTR MOVX @R0, A MOVX @R1, A MOVX @DPTR, A MOV C, bit MOV bit, C ORL A, R0 ORL A, R1 ORL A, R2 ORL A, R3 ORL A, R4
HEX Op-Code 0B 0C 0D 0E 0F 06 07 05 A3 73 60 70 A7 76 77 F5 88 89 8A 8B 8C 8D 8E 8F 86 87 85 75 90 93 83 E2 E3 E0 F2 F3 F0 A2 92 48 49 4A 4B 4C
Bytes 1 1 1 1 1 1 1 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1
Machine Cycles 1 1 1 1 1 1 1 2 2 2 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1
Instruction MOV R7, direct MOV R0, #data MOV R1, #data MOV R2, #data MOV R3, #data MOV R4, #data MOV R5, #data MOV R6, #data MOV R7, #data MOV @R0, A MOV @R1, A MOV @R0, direct RL A RLC A RR A RRC A SETB C SETB bit SWAP A SJMP rel SUBB A, R0 SUBB A, R1 SUBB A, R2 SUBB A, R3 SUBB A, R4 SUBB A, R5 SUBB A, R6 SUBB A, R7 SUBB A, @R0 SUBB A, @R1 SUBB A, direct SUBB A, #data XCH A, R0 XCH A, R1 XCH A, R2 XCH A, R3 XCH A, R4 XCH A, R5 XCH A, R6 XCH A, R7 XCH A, @R0 XCH A, @R1 XCHD A, @R0 XCHD A, @R1
HEX Op-Code AF 78 79 7A 7B 7C 7D 7E 7F F6 F7 A6 23 33 03 13 D3 D2 C4 80 98 99 9A 9B 9C 9D 9E 9F 96 97 95 94 C8 C9 CA CB CC CD CE CF C6 C7 D6 D7
Bytes 2 2 2 2 2 2 2 2 2 1 1 2 1 1 1 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1
Machine Cycles 2 2 2 2 2 2 2 2 2 1 1 2 1 1 1 1 1 2 1 3 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1
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W925EP01/ W925EP01FG
Table 6 Instruction Timing for W925EP01, continued
Instruction ORL A, R5 ORL A, R6 ORL A, R7 ORL A, @R0 ORL A, @R1 ORL A, direct ORL A, #data ORL direct, A ORL direct, #data ORL C, bit ORL C, /bit PUSH direct POP direct RET RETI
HEX Op-Code 4D 4E 4F 46 47 45 44 42 43 72 A0 C0 D0 22 32
Bytes 1 1 1 1 1 2 2 2 3 2 2 2 2 1 1
Machine Cycles 1 1 1 1 1 2 2 2 3 2 2 2 2 2 2
Instruction XCH A, direct XRL A, R0 XRL A, R1 XRL A, R2 XRL A, R3 XRL A, R4 XRL A, R5 XRL A, R6 XRL A, R7 XRL A, @R0 XRL A, @R1 XRL A, direct XRL A, #data XRL direct, A XRL direct, #data
HEX Op-Code C5 68 69 6A 6B 6C 6D 6E 6F 66 67 65 64 62 63
Bytes 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3
Machine Cycles 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3
6.5
Power Management
The W925EP01 has 3 operation mode, normal mode, idle mode and power down mode to manage the power consumption. Normal Mode Normal mode is used in the normal operation status. All functions can be worked in the normal mode. Idle Mode The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the idle bit is the last instruction that will be executed before the device goes into Idle Mode. In the Idle mode, the clock to the CPU is halted, but not to the Interrupt, Timer, Watchdog timer, Divider, Comparator and CID blocks. This forces the CPU state to be frozen; the Program counter, the Stack Pointer, the Program Status Word, the Accumulator and the other registers hold their contents. The port pins hold the logical states they had at the time Idle was activated. The Idle mode can be terminated in two ways. Since the interrupt controller is still active, the activation of any enabled interrupt can wake up the processor. This will automatically terminate the idle mode and clear the idle bit. And if bit IDLT (PCON.4) is cleared the Interrupt Service Routine (ISR) will be executed, else the idle mode is released directly without any execution of ISR. After the ISR, execution of the program will continue from the instruction, which put the device into idle mode. The Idle mode can also be exited by activating the reset. The device can be put into reset by either applying a low on the external RESET pin or a power on/fail reset condition or a Watchdog timer reset. The external reset pin has to be held low for at least two machine cycles i.e. 8 clock periods to be recognized as a valid reset. In the reset, condition the program counter is reset to 0000h and all the SFRs are set to the reset condition. Since the clock is still running in the period of external reset therefore the instruction is executed immediately. In the Idle mode, the Watchdog timer continues to run, and if enabled, a time-out will cause a watchdog timer interrupt, which will wake up the device. The software must reset the Watchdog timer in order to preempt the reset, which will occur after 512 clock periods of the time-out. Publication Release Date: Apr. 10, 2006 Revision A2
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W925EP01/ W925EP01FG
Power down Mode The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does this will be the last instruction to be executed before the device goes into Power Down mode. In the Power Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely stopped and the power consumption is reduced to the lowest possible value. The port pins output the values held by their respective SFRs. The W925EP01 will exit the Power Down mode by reset or external interrupts or ring detected. An external reset can be used to exit the Power down state. The low on RESET pin terminates the Power Down mode, and restarts the clock. The on-chip hardware will now provide a delay of 65536 clocks, which is used to provide time for the oscillator to restart and stabilize. Once this delay is complete, an internal reset is activated and the program execution will restart from 0000h. In the Power down mode, the clock is stopped, so the Watchdog timer cannot be used to provide the reset to exit Power down mode. The W925EP01 can be woken from the Power Down mode by forcing an external interrupt pin activated and ring detected, provided the corresponding interrupt is enabled, while the global enable (EA) bit is set. While the power down is released, the device will experience a warm-up delay of 65536 clock cycles to ensure the stabilization of oscillation. Then device executes the interrupt service routine for the corresponding external interrupt or CID interrupt. After the interrupt service routine is completed, the program returns to the instruction after the one, which put the device into Power Down mode and continues from there. When RGSL (PMR.5) bit is set to 1, the CPU will use the internal RC oscillator instead of crystal to exit Power Down mode. The micro-controller will automatically switch from RC oscillator to crystal after a warm-up delay of 65536 crystal clocks. The RC oscillator runs at approximately 2-4 MHz. Using RC oscillator to exit from Power Down mode saves the time for waiting crystal start-up. It is useful in the low power system which usually be awakened from a short operation then returns to Power Down mode.
6.6
Reset
The user has several hardware related options for placing the W925EP01 into reset condition. In general, most register bits go to their reset value irrespective of the reset condition, but there are few flags that initial states are dependant on the source of reset. User can recognize the cause of reset by reading the flags. There are three ways of putting the device into reset state. They are External reset, Power on reset and Watchdog reset. External Reset The device continuously samples the RESET pin at state C4 of every machine cycle. Therefore, the RESET pin must be held for at least 2 machine cycles to ensure detection of a valid RESET high. The reset circuitry then synchronously applies the internal reset signal. Thus, the reset is a synchronous operation and requires the clock to be running to cause an external reset. Once the device is in reset condition, it will remain so as long as RESET is 1. Even after RESET is deactivated, the device will continue to be in reset state for up to two machine cycles, and then begin program execution from 0000h. There is no flag associated with the external reset condition. However, since some flags indicate the cause of other two reset, the external reset can be considered as the default reset if those two flags are cleared. Watchdog Timer Reset The Watchdog timer is a free running timer with programmable time-out intervals. The user can reset the watchdog timer at any time to avoid producing the flag WDIF. If the Watchdog reset is enabled and the flag WDIF is set high, the watchdog timer reset is performed after the additional 512 clocks come. This places the device into the reset condition. The reset condition is maintained by hardware for two machine cycles. Once the reset is removed, the device will begin execution from 0000h. - 46 -
W925EP01/ W925EP01FG
6.7 Interrupt
The W925EP01 has a two priority levels interrupt structure with 12 interrupt sources. Each of the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts can be globally enabled or disabled. Interrupt Sources The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, depending on bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags, which are checked to generate the interrupt. In the edge triggered mode of the INT0 and the INT1 inputs are sampled in every machine cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected and the interrupts request flag IEx in TCON is set. The flag bit requests the interrupt. Since the external interrupts are sampled every machine cycle, they have to be held high or low for at least one complete machine cycle. The IEx flag is automatically cleared when the service routine is called. If the level triggered mode is selected, then the requesting source has to hold the pin low until the interrupt is serviced. The IEx flag will not be cleared by the hardware on entering the service routine. If the interrupt continues to be held low even after the service routine is completed, then the processor may acknowledge another interrupt request from the same source. Note that the external interrupts INT2 to INT3 are edge triggered only. The TF0, TF1 flags generate the Timer 0, 1 Interrupts. These flags are set by the overflow in the Timer 0, Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware when the timer interrupt is serviced. The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the time-out count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the enable bit EIE.5 enables the interrupt, then an interrupt will occur. The Serial block can generate interrupts on reception or transmission. There are two interrupt sources from the Serial block, which are obtained by the RI and TI bits in the SCON SFR and SF1 in the SCON1 SFR. RI and TI are not automatically cleared by the hardware, and the user will have to clear these bits using software, SF1 is cleared automatically when the serial port1 interrupt is serviced. The divider interrupt is generated by DIVF that is set when divider overflows. DIVF is set by hardware and cleared when divider interrupt is serviced. The divider interrupt is enable/disable if the bit EDIV is high/low. The comparator interrupt is produced by COMPF, which is set when the RESC bit is changed from low to high. RESC, which is the real-time result of comparator, set when the voltage of reference input is higher than the voltage of analog input. The CID interrupt is generated by CIDF. The CIDF is a logic OR output of all CID flags which are set by hardware and cleared by software. The structure of the CID flags is shown in Figure 6-4. Each of the individual interrupts can be enabled or disabled by setting or clearing the corresponding bits in the IE and EIE SFR. A bit EA, which is located in IE.7, is a global control bit to enable/disable the all interrupt. When bit EA is zero all interrupts are disabling and when bit EA is high, each interrupt is enabled individually by the corresponding bit.
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
RNGF FDRF ALGOF DTMFDF FSF
CIDF D
System clock Clear by software
R
Figure 6-4 The Structure of CID Flags
Priority Level Structure There are two priority levels for the interrupts, high and low. The interrupt sources can be individually set to either high or low levels. Naturally, a higher priority interrupt cannot be interrupted by a lower priority interrupt. However there exists a pre-defined hierarchy amongst the interrupts themselves. This hierarchy comes into play when the interrupt controller has to resolve simultaneous requests having the same priority level. This hierarchy is defined as shown below; the interrupts are numbered starting from the highest priority to the lowest.
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W925EP01/ W925EP01FG
Table 7 Interrupt table.
INTERRUPT FLAG NAME FLAG LOCATION EN BIT EN BIT LOCATION PRIORITY
1
FLAG CLEARED INTERRUPT BY VECTOR
External interrupt 0 Timer0 overflow External interrupt 1 Timer1 overflow Serial port0 Serial port1 External interrupt 2 External interrupt 3 CID Divider overflow Compare difference Watchdog timer
IE0 TF0 IE1 TF1 RI TI SF1 IE2 IE3 CIDF DIVF COMPF WDIF
TCON.1 TCON.5 TCON.3 TCON.7 SCON.0 SCON.1 SCON1.7 EXIF.0 EXIF.1 EXIF.2 EXIF.3 EXIF.4 WDCON.3
EX0 ET0 EX1 ET1 ES0 ES1 EX2 EX3 ECID EDIV ECOMP EWDI
IE.0 IE.1 IE.2 IE.3 IE.4 IE.6 EIE.0 EIE.1 EIE.2 EIE.3 EIE.4 EIE.5
(higest) 2 3 4 5 6 7 8 9 10 11
12
hardware + software hardware + software hardware + software hardware + software hardware + software hardware + software hardware + software hardware + software software hardware + software hardware + software software
03h 0Bh 13h 1Bh 23h 3Bh 43h 4Bh 53h 5Bh 63h 6Bh
(lowest)
Ps: The flags marked as the italic font are not bit-addressable. The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will execute an internally generated LCALL instruction which will vector the process to the appropriate interrupt vector address. The conditions for generating the LCALL are 1. An interrupt of equal or higher priority is not currently being serviced. 2. The current polling cycle is the last machine cycle of the instruction currently being executed. 3. The current instruction does not involve a write to IP, IE, EIP or EIE registers and is not a RETI. If any of these conditions is not met, then the LCALL will not be generated. The polling cycle is repeated every machine cycle, with the interrupts being sampled in the same machine cycle. If an interrupt flag is active in one cycle but not responded to, and is not active when the above conditions are met, the denied interrupt will not be serviced. This means that active interrupts are not remembered. Note that every polling cycle is new. Execution continues from the vectored address until an RETI instruction is executed. On execution of the RETI instruction, the processor pops out the top content of Stack to the PC. The processor is not notified anything if the content of stack was changed. Note that a RET instruction would perform exactly the same process as a RETI instruction, but it would not inform the Interrupt Controller that the interrupt service routine is completed, and would leave the controller still thinking that the service routine is underway.
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
6.8 Programmable Timers/Counters
The W925EP01 has two 16-bit timer/counters. There are two 8-bit registers to perform a 16-bit counting register in every timer/counter. In timer/counter 0, TH0 is the upper 8 bits register and TL0 is the lower 8 bits register. Similarly, timer/counter 1 has two 8-bit registers, TH1 and TL1. Each timer/counter has 4 kinds of clock sources, which are Fosc/4, Fosc/64, Fosc/1024 and Fs. There are 3 operating modes in each timer/counter 0 and 1. The operating modes of timer/counter0 are identical to timer/counter1. The overflow signal of each timer/counter is sampled at phase 2 in every system machine cycle, therefore when the system clock and the timer/counter clock both are from suboscillator, if the overflow frequency is higher than Fs/4 the overflow flag cannot be sampled correctly. Only one overflow flag can be sampled in a machine cycle others will be missed. MODE 0 In Mode 0, the timer/counters act as 13-bit timer/counters. The 13 bits consist of 8 bits of THx and lower 5 bits of TLx. The upper 3 bits of TLx are ignored. The negative edge of the clock causes the content of the TLx register to increase one. When the fifth bit in TLx moves from 1 to 0, then the count in the THx register is incremented. When the count in THx moves from FFh to 00h, then the overflow flag TFx is set. The counted input is enabled only if TRx is set and either GATE=0 or INTx =1. When C/ T is set to 0, then it will count clock cycles, and if C/ T is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and T1 (P3.5) for timer 1. When the 13-bit count reaches 1FFFh, the next count will cause it to rollover to 0000h. The timer overflow flag TFx of the relevant timer is set and if enabled an interrupts will occur. Note that when they are used as a timer, the bits of the CKCON1 select the time-base. MODE1 Mode 1 is similar to Mode 0 except that the counting register forms a 16-bit counter, rather than a 13 bit counter.
TM0=CKCON1.2, CKCON1.3 (TM1=CKCON1.4, CKCON1.5) Fosc/4 Fosc/64 Fosc/1024 Fs T0 = P3.4 (T1 = P3.5) TR0 = TCON.4 (TR1 = TCON.6) GATE = TMOD.3 (GATE = TMOD.7) INT0 = P3.2 (INT1 = P3.3)
00 01 10 11
mux
C/T = TMOD.2 (C/T = TMOD.6) 0 1 0 4 TL0 (TL1)
M1,M0 = TMOD.1,TMOD.0 (M1,M0 = TMOD.5,TMOD.4) 00 7 01 0 TH0 (TH1) 7
TFx TF0 (TF1)
Interrupt
PS: Functions of timer1 are shown in brackets
Figure 6-5 Mode 0 & Mode 1 of Timer/Counter 0 & 1
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W925EP01/ W925EP01FG
MODE 2 Mode 2 is the Auto Reload Mode. In mode 2, TLx acts as an 8-bit count register, while THx holds the reload value. When the TLx register overflows from FFh to 00h, the TFx bit is set and TLx is reloaded with the content of THx, and the counting process continues from the reloaded TLx. The reload operation leaves the content of the THx register unchanged. The TRx bit and the proper setting of GATE and INTx pins controll counting. BUZZER In mode 2, timer 0 can be use to output an arbitrary frequency to the BUZ pin by programming bit6 and bit7 of CKCON2. BUZ pin can be configured as key tone (KT) output by set BUZSL to high. When disable buzzer output by clearing ENBUZ to low, the BUZ output is in floating status. In the case where timer 0 clock input is FT, the desired frequency for BUZ output = FT / (255 - preset value + 1) / 2 (HZ).
CKCON2.5, CKCON2.4 Low 512Hz 1024Hz 2048Hz
00 01 10 11
TM0=CKCON1.2, CKCON1.3 (TM1=CKCON1.4, CKCON1.5) Fosc/4 Fosc/64 Fosc/1024 Fs
00 01 10 11
mux
CKCON2.6 CKCON2.7 =BUZSL =ENBUZ KT
1/2 From TM0
Pin BUZ
floating
mux
C/T = TMOD.2 (C/T = TMOD.6) 0 FT 1
TL0 (TL1)
T0 = P3.4 (T1 = P3.5) TR0 = TCON.4 (TR1 = TCON.6) GATE = TMOD.3 (GATE = TMOD.7) INT0 = P3.2 (INT1 = P3.3)
0
7
TFx
TF0 (TF1)
Interrupt
0
TH0 (TH1)
7
PS: Functions of timer1 are shown in brackets
Figure 6-6 Mode 2 of Timer/Counter 0 & 1
When FT equals 32768 Hz, depending on the preset value of TM0, the BUZ pin will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the tone frequency and the preset value of TM0 is shown in the table below.
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
Table 8 The relation between the tone frequency and the preset value of TM0
3rd octave
Tone frequency TM0 preset value & BUZ frequency 83H 8AH 90H 97H 9DH A2H A7H ACH B1H B6H BAH BEH 131.07 138.84 146.28 156.03 165.49 174.30 184.09 195.04 207.39 221.40 234.05 248.24
4th octave
Tone frequency 261.63 277.18 293.66 311.13 329.63 349.23 369.99 392.00 415.30 440.00 466.16 493.88 TM0 preset value & BUZ frequency C1H C5H C8H CBH CEH D1H D4H D6H D9H DBH DDH DF H 260.06 277.69 292.57 309.13 327.68 348.58 372.35 390.08 420.10 442.81 468.11 496.48 523.25 554.37 587.33 622.25 659.26 698.46 739.99 783.99 830.61 880.00 932.23 987.77
5th octave
Tone frequency TM0 preset value & BUZ frequency E1H E3H E4H E6H E7H E9H EAH EBH ECH EDH EEH EFH 528.51 564.96 585.14 630.15 655.36 712.34 744.72 780.19 819.20 862.84 910.22 963.76
C C# D D E F F
#
130.81 138.59 146.83 155.56 164.81 174.61 # 185.00 196.00 207.65 220.00 233.08 246.94
T O N E
G G# A A# B
Note: Central tone is DB (440 Hz).
WATCHDOG TIMER The Watchdog timer is a free-running timer that can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. It is a set of dividers that divides the system clock. The divider output is selectable and determines the time-out interval. In the condition of the timer-out expiring, the WDT interrupt and WDT reset may be executed if the corresponding enables control bits are set. The interrupt will occur if the individual interrupt enable and the global enable are set. The interrupt and reset functions are independent of each other and may be used separately or together depending on the users software.
Fsub Fosc
1 12
WD1,WD0
WDIF EWDI(EIE.5)
Interrupt
WFS(WDCON.4)
13
15
00 01 10 11 Time-out
WTRF
16
18
selector
Reset Watchdog RWT (WDCON.0) 19 21
512 clock delay
Reset
Enable Watchdog timer reset EWT(WDCON.1)
Figure 6-7Watchdog Timer
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W925EP01/ W925EP01FG
The Watchdog timer should first be restarted by using RWT. This ensures that the timer starts from a known state. The RWT bit is used to restart the watchdog timer. This bit is self-clearing, i.e. after writing a 1 to this bit the software will automatically clear it. The watchdog timer will now count clock cycles. The time-out interval is selected by the two bits WD1 and WD0 (CKCON.7 and CKCON.6). When the selected time-out occurs, the Watchdog interrupt flag WDIF (WDCON.3) is set. After the time-out has occurred, the watchdog timer waits for an additional 512 clock cycles. The software must issue a RWT to reset the watchdog before the 512 clocks have elapsed. If the Watchdog Reset EWT (WDCON.1) is enabled, then 512 clocks after the time-out, if there is no RWT, a system reset due to Watchdog timer will occur. This will last for two machine cycles, and the Watchdog timer reset flag WTRF (WDCON.2) will be set. This indicates to the software that the watchdog was the cause of the reset. When used as a simple timer, the reset and interrupt functions are disabled. The timer will set the WDIF flag each time the timer completes the selected time interval. The WDIF flag is polled to detect a time-out and the RWT allows software to restart the timer. The Watchdog timer can also be used as a very long timer. The interrupt feature is enabled in this case. Every time the time-out occurs an interrupt will occur if the global interrupt enable EA is set. Table 9 Time-out values for the Watchdog timer
WD1 WD0 WATCHDOG INTERVAL NUMBER OF CLOCKS FOSC= 4 MHZ FOSC= 32768 HZ RESET OF CLOCKS (N CLOCK+512)
0 0 1 1
0 1 0 1
2 2 2 2
12 15 18 21
4096 32786 262144 2097152
1.024mS 8.192mS 65.536mS 524.288mS
0.125 S 1S 8S 64 S
4608 33280 262656 2097664
The Watchdog timer will be disabled by a power-on/fail reset. The Watchdog timer reset does not disable the watchdog timer, but will restart it. In general, software should restart the timer to put it into a known state. The control bits that support the Watchdog timer are discussed below. WATCHDOG CONTROL WDIF: WDCON.3 - Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the watchdog timer. If the Watchdog interrupt is enabled (EIE.5), then an interrupt will occur (if the global interrupt enable is set and other interrupt requirements are met). Software or any reset can clear this bit. WTRF: WDCON.2 - Watchdog Timer Reset flag. This bit is set whenever a watchdog reset occurs. This bit is useful for determined the cause of a reset. Software must read it, and clear it manually. A Power-fail reset will clear this bit. If EWT = 0, then this bit will not be affected by the watchdog timer. EWT: WDCON.1 - Enable Watchdog timer Reset. This bit when set to 1 will enable the Watchdog timer reset function. Setting this bit to 0 will disable the Watchdog timer reset function, but will leave the timer running
RWT: WDCON.0 - Reset Watchdog Timer. This bit is used to clear the Watchdog timer and to restart it. This bit is self-clearing, so after the software writes 1 to it the hardware will automatically clear it. If the Watchdog timer reset is enabled, then the RWT has to be set by the user within 512 clocks of the time-out. If this is not done then a Watchdog timer reset will occur. Publication Release Date: Apr. 10, 2006 Revision A2
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W925EP01/ W925EP01FG
CLOCK CONTROL WD1, WD0: CKCON.7, CKCON.6 - Watchdog Timer Mode select bits. These two bits select the timeout interval for the watchdog timer. The reset time is longer 512 clocks time than the interrupt time-out value. The default Watchdog time-out is 2
12
clocks, which is the shortest time-out period.
6.9
Serial Port
SERIAL PORT0 Serial port0 in the W925EP01 is a full duplex port. The W925EP01 provides the user with additional features such as the Frame Error Detection and the Automatic Address Recognition. The serial port0 are capable of synchronous as well as asynchronous communication. In Synchronous mode the W925EP01 generates the clock and operates in a half duplex mode. In the asynchronous mode, full duplex operation is available. This means that it can simultaneously transmit and receive data. The transmit register and the receive buffer are both addressed as SBUF Special Function Register. However any write to SBUF will be to the transmit register, while a read from SBUF will be from the receiver buffer register. The serial port0 can operate in four different modes as described below. MODE 0 This mode provides synchronous communication with external devices. In this mode, serial data is transmitted and received on the RXD line. TXD is used to transmit the shift clock that is provided by the W925EP01 whether the device is transmitting or receiving. This mode is therefore a half duplex mode of serial communication. In this mode, 8 bits are transmitted or received per frame. The LSB is transmitted or received first. The baud rate is fixed at 1/12 or 1/4 of the oscillator frequency. This baud rate is determined by the SM2 bit (SCON.5). When bit SM2 is set to zero, the transceiver rate of serial rate is 1/12 of the clock. When bit SM2 is set to one, the transceiver rate of serial rate is 1/4 of the clock. The functional block diagram is shown below. Data enters and leaves the Serial port on the RxD line. The TxD line is used to output the shift clock. The shift clock is used to shift data into and out of the W925EP01 and the device at the other end of the line. Any instruction that causes a write to SBUF will start the transmission. The shift clock will be activated and data will be shifted out on the RxD pin until all 8 bits are transmitted. If SM2 = 1, then the data on RxD will appear 1 clock period before the falling edge of shift clock on TxD. The clock on TxD then remains low for 2 clock periods, and then goes high again. If SM2 = 0, the data on RxD will appear 3 clock periods before the falling edge of shift clock on TxD. The clock on TxD then remains low for 6 clock periods, and then goes high again. This ensures that at the receiving end the data on RxD line can either be clocked on the rising edge of the shift clock on TxD or latched when the TxD clock is low.
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W925EP01/ W925EP01FG
Fosc/2 Write to SBUF 12 4
TX START TX CLOCK
Internal Data Bus
PARIN LOAD CLOCK
SOUT
RXD P3.0 Alternate Output Function
TX SHIFT TI
Transmit Shift Register Serial Port Interrupt
SM2 0 1
SERIAL CONTROLLE
RX CLOCK RI SHIFT CLOCK LOAD SBUF RX SHIFT CLOCK PAROUT SIN
RI REN RXD P3.0 Alternate Iutput function
RX START
TXD P3.1 Alternate Output function Read SBUF
SBUF
Internal Data Bus
Receive Shift Register
Figure 6-8 Serial Port 0 Mode 0
MODE 1 In Mode 1, the full duplex asynchronous mode is used. Serial communication frames are made up of 10 bits that are transmitted on TXD and received on RXD. The 10 bits consist of a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8(SCON.3). The baud rate in this mode is variable. The serial baud rate can be programmed as 1/16 or 1/32 of the Timer 0 or 1 overflow, or 1/16 of the baud rate generator counter (BG-counter) overflow. In mode 1, the SM2 (SCON.5) must be cleared. Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at C1 following the first rollover of divide by 16 bit counter. The next bit is placed on TxD pin at C1 following the next rollover of the divide by 16 bit counter. Thus, the transmission is synchronized to the divide by 16 bit counter and not directly to the write to SBUF signal. After all 8 bits data has been transmitted, the stop bit is transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD pin. This will be at the 10th rollover of the divide by 16 bit counter after a write to SBUF. Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD line, sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the divide by 16 bit counter is immediately reset. This helps to align the bit boundaries with the rollovers of the divide by 16 bit counter. The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a best of three bases. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise rejection feature of the serial port. If the first bit detected after the falling edge of RxD pin is not 0, then this indicates an invalid start bit, and the reception is immediately aborted. The serial port again looks for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also detected and shifted into the SBUF. Publication Release Date: Apr. 10, 2006 Revision A2
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W925EP01/ W925EP01FG
After shifting in 8 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded and RI is set. However, certain conditions must be met before the loading and setting of RI can be done. 1. RI must be 0 and 2. Either SM2 = 0, or the received stop bit = 1. If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise, the received frame may be lost. After the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the RxD pin.
Timer 0 Overflow
0 1
Timer 1 BG Counter Overflow Overflow
SFS(PCON.5)
Transmit Shift Register
STOP
2 SMOD (PCON.7)
Write to SBUF 1
TX START
Internal Data Bus
PARIN START LOAD CLOCK SOUT
TXD
0 0
TX SHIFT TI
TCKEN
1
16
TX CLOCK
RCKEN
0
1
16
SERIAL CONTROLLER
RX CLOCK RX START
RI
Serial Port Interrupt
SAMPLE
1-TO-0 DETECTOR
LOAD SBUF RX SHIFT CLOCK PAROUT SBUF RB8
Read SBUF Internal Data Bus
RXD
BIT DETECTOR
SIN
D8
Receive Shift Register
Figure 6-9 Serial Port 0 Mode 1
MODE 2 This mode uses 11 bits in asynchronous full-duplex communication. The functional description is shown in the figure below. The frame consists of one start bit (0), 8 data bits (LSB first), a programmable 9th bit (TB8) and a stop bit (0). The 9th bit received is put into RB8. The baud rate is programmable to 1/6 or 1/32 of the system clock which is determined by the SMOD (PCON.0). Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at C1 following the first rollover of the divide by 16 bit counter. The next bit is placed on TxD pin at C1 following the next rollover of the divide by 16 bit counter. Thus the transmission is synchronized to the divide by 16 bit counter, and not directly to the write to SBUF signal. After all 9 bits data has been transmitted, then the stop bit is transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD pin. This will be at the 11th rollover of the divide by 16 bit counter after a write to SBUF. Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD line, sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the divide by 16 bit counter is immediately reset. This helps to align the bit boundaries with the rollovers of the divide by 16 bit counter. The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a best of three bases. The bit detector samples the RxD pin, at the 8th, 9th - 56 -
W925EP01/ W925EP01FG
and 10th counter states. By using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise rejection feature of the serial port. If the first bit detected after the falling edge of RxD pin, is not 0, then this indicates an invalid start bit, and the reception is immediately aborted. The serial port again looks for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also detected and shifted into the SBUF. After shifting in 9 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded and RI is set. However certain conditions must be met before the loading and setting of RI can be done. 1. RI must be 0 and 2. Either SM2 = 0, or the received stop bit = 1. If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise, the received frame may be lost. After the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the RxD pin.
Fosc/2
2
SMOD (PCON.7)
TB8
D8 STOP PARIN START LOAD CLOCK
Write to SBUF 1
Internal Data Bus
SOUT
TXD
0
TX START
16 16 SAMPLE
TX CLOCK
TX SHIFT
Transmit Shift Register
TI
SERIAL CONTROLLER RX CLOCK
RI
Serial Port Interrupt Read SBUF
CLOCK PAROUT
1-TO-0 DETECTOR
RX START
LOAD SBUF RX SHIFT SBUF RB8
RXD
BIT DETECTOR
SIN
D8
Internal Data Bus
Receive Shift Register
Figure 6-10 Serial Port 0 Mode 2
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W925EP01/ W925EP01FG
MODE 3 This mode is similar to Mode 2 in all respects, except that the baud rate is programmable. The user must first initialize the Serial related SFR SCON before any communication can take place. This involves selection of the Mode and baud rate. The Timer 0 or 1 or baud rate generator (BG) should also be initialized if modes 1 and 3 are used. In all four modes, transmission is started by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. This will generate a clock on the TxD pin and shift in 8 bits on the RxD pin. Reception is initiated in the other modes by the incoming start bit if REN = 1. The external device will start the communication by transmitting the start bit. Table 10 Serial Ports Modes
SM1 SM0 MODE TYPE BAUD CLOCK FRAME SIZE START BIT STOP BIT 9TH BIT FUNCTION
0 0 1 1
0 1 0 1
0 1 2 3
Synch. Asynch. Asynch. Asynch.
4 or 12 TCLKS Timer 0 or 1 16 or 32 TCLKS Timer 0 or 1
8 bits 10 bits 11 bits 11 bits
No 1 1 1
No 1 1 1
None None 0, 1 0, 1
Fosc
BGEN= BGCON.0
BG_Counter
BG_counter overflow
BG
Figure 6-11 Serial Port0 Baud Rate Generator Mode
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W925EP01/ W925EP01FG
Timer 0 Overflow
0 1
Timer 1 Overflow
BG Counter Overflow
STOP
TB8 Internal Data Bus
D8 PARIN START LOAD CLOCK SOUT
SFS(PCON.5)
2 SMOD (PCON.7)
Write to SBUF 1
TX START
TXD
0 0
TX SHIFT TI
Transmit Shift Register
TCKEN
1
16
TX CLOCK
RCKEN
0
1
16
SERIAL CONTROLLER
RX CLOCK
RI
Serial Port Interrupt
SAMPLE
1-TO-0 DETECTOR
RX START
LOAD SBUF RX SHIFT CLOCK PAROUT SBUF RB8
Read SBUF Internal Data Bus
RXD
BIT DETECTOR
SIN
D8
Receive Shift Register
Figure 6-12 Serial Port Mode 3
Framing Error Detection A Frame Error occurs when a valid stop bit is not detected. This could indicate incorrect serial data communication. Typically, the frame error is due to noise and contention on the serial communication line. The W925EP01 has the facility to detect such framing errors and set a flag which can be checked by software. The Frame Error FE bit is located in SCON.7. This bit is normally used as SM0; therefore, the bit is named as SM0/FE. There are actually two separate flags, one for SM0 and the other for FE. The flag that is actually accessed as SCON.7 is determined by SMOD0 (PCON.6) bit. When SMOD0 is set to 1, then the FE flag is indicated in SM0/FE. When SMOD0 is set to 0, then the SM0 flag is indicated in SM0/FE. The FE bit is set to 1 by hardware but must be cleared by software. Note that SMOD0 must be 1 while reading or writing to FE. If FE is set, then any following frames received without any error will not clear the FE flag. The clearing has to be done by software. SERIAL PORT1 The P4.0 and P4.1 can be used as an 8-bit serial input/output port1. P4.0 is the serial port1 clock I/O pin and P4.1 is the serial port1 data I/O pin. The serial port1 is controlled by SCON1 register which is described as below. SF1: Serial port1 interrupt flag. When 8-bits data transited completely, SF1 is set by hardware. SF1 is cleared when serial interrupt routine is executed or cleared by software.
REGON: Regulator on/off control. 0 will disable regulator, 1 will enable regulator. Publication Release Date: Apr. 10, 2006 Revision A2
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W925EP01/ W925EP01FG
REN1: SFQ: SEDG: Set REN1 from 0 to 1 to start the serial port to receive 8-bit serial data. SFQ=0 Serial clock output frequency is equal to fosc /2 SFQ=1 Serial clock output frequency is equal to fosc /256 SEDG=0 Serial data latched at falling edge of clock, SCLK=Low initially. SEDG=1 Serial data latched at rising edge of clock, SCLK=High initially CLKIO: CLKIO=0 P4.0 (SCLK) work as output mode CLKIO=1 P4.0 (SCLK) work as input mode SIO: SIO=0 P4.0 & P4.1 work as normal I/O pin SIO=1 P4.0 & P4.1 work as Serial port1 function Any instruction causes a write to SBUF1 will start the transmission of serial port1. As the REN1 is from 0 to 1, the serial port1 begins to receive a byte into SBUF1 in the frequency of the serial clock. REN1 could be cleared by software after receive function begins. The LSB is transmitted/ received first. The I/O mode of serial clock pin is controlled by CLKIO. User has to take care the initial state of the serial port pins.
C1 C2 C3 C4 REN1
SEDG=1, rising latch
P4.0 P4.0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
SEDG=0, falling latch
SF1
Data Input
P4.1
NOTE: The serial clock frequency is fosc/2
Figure 6-6 Timing of the Serial port1 Input Function
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W925EP01/ W925EP01FG
C1 C2 C3 C4 Ins. P4.0 P4.0
serial out instruction
SEDG=1, falling changed
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
SEDG=0, rising changed
SF1 P4.1
Data output
NOTE: The serial clock frequency is fosc/2
Figure 6-7 Timing of the Serial port1 Output Function
6.10 Comparator
A built-in comparator can compare the analog signal. There is an analog input path from pin VNEG. And one reference input from pin VPOS. When the voltage of positive input is higher than the negative input, the comparator output will be high. The RESEC (COMPR.3) is the result of the comparison. An internal rising signal on RESC produces interrupt flag of COMPF (EXIF.4). The flag COMPF is cleared when comparator interrupt routine is executed or cleared by software. Set COMPEN to enable the comparator function.
VNEG(P4.2) D VPOS(P4.4) REF1 REF
X.XV REGULATOR EN C3 RESET RESC
Clr
D
CK COMPF=0
CK
Clr
EXIF.4 (COMPF)
COMPEN SCON1.5(REGON)
Figure 6-8 The Configuration of Comparator
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W925EP01/ W925EP01FG
6.11 DTMF Generator
W925EP01 provides a DTMF generator, which outputs the dual tone multi-frequency signal to the DTMF pin. The DTMF generator can work well at the operating frequency of 4M/8MHz. A DTMF generator register DTMFG controls the DTMF output and specifies the desired low/high frequency. The tones are divided into two groups (low group and high group). When the generator is disabled, the DTMF pin is in tri-state. The relation between the DTMF signal and the corresponding touch-tone keypad is shown in Figure 6-9.
C1 R1 R2 R3 R4 1 4 7 *
C2 2 5 8 0
C3 3 6 9 #
C4 A B C D
ROW/COL
FREQUENCY
R1 R2 R3 R4 C1 C2 C3 C4
697 Hz 770 Hz 852 Hz 941 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz
Figure 6-9 The Relation Between DTMF and Keypad
Bit:
7 CASGE
6 DTGE
5 HE
4 LE
3 L1
2 L0 Address: BAh
1 H1
0 H0
Mnemonic: DTMFG CASGE: Enable CAS tone output to DTMF pin. DTGE: Enable dual tone output to DTMF pin. HE: Enable CAS/DTMF high group frequency output. LE: Enable CAS/DTMF low group frequency output.
L1 L0 H1 H0
DTMF SELECTED TONE
x x x x 0 0 1 1
x x x x 0 1 0 1
0 0 1 1 x x x x
0 1 0 1 x x x x
1209Hz 1336Hz 1477Hz 1633Hz 697Hz 770Hz 852Hz 941Hz
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W925EP01/ W925EP01FG
6.12 FSK Generator
W925EP01 provides a FSK generator, which outputs the FSK signal to the DTMF pin. The FSK output share with DTMF output pin. It can out FSK signal with 1200Hz baud rate of ITU-T V.23 or Bellcore 202 signal. A FSK transmit data register (FSKTB) specifies the desired output data. The FSK Transmit Control Register (FSKTC) can control whether the FSK signal will be output or not. The relation timing is shown in Figure 6-10
Enable signal (FTE) Latch clock [FSF] Data latch Flag (FDS) Data (FSKTB) bit0 FSK Signal (DTMF pin) Auto clear
Interrupt occur when rising edge
1 Hi-Z 1
0
1
1
0
0 Hi-Z
0
1
1
0
833us
Figure 6-10 FSK Modulator
FSK TRANSIMT CONTROL REGISTER Bit: 7 FTE Mnemonic: FSKTC FTE: FTM: FDS: FSK transmit Enable. Enable=1, Disable=0 FSK signal Standard. Bellcore 202=1, V.23=0 FSK data sending status 6 FTM 5 FDS 4 3 -
(initial=00H) 2 1 LO1 0 LO0
Address: C6h
LO0, LO1: FSK transmitting level option FSK output level 150mV 125mV 100mV 75mV LO1 0 0 1 1 LO0 0 1 0 1
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W925EP01/ W925EP01FG
FSK TRANSMIT DATA BUFFER Bit: 7 Mnemonic: FSKTB FSKTB.0: Only this bit will be latched and send out as FSK signal When FTE enable will set the FDS to high to enable the internal latch clock in 1200Hz. When FDS is in high state, FSKTB bit0 will be sent out by FSK modulator at the rising edge of latch clock. FDS could be cleared by software to inform no more data will be sent out after the last bit is sent completely. If the FDS is cleared then FTE will become low at next rising latch clock to disable FSK modulator and clear FDS by hardware automatically. When FTE is set, FSK modulation flag (FSF) will be set at every rising edge of latch clock to produce an interrupt shared with CID interrupt routine. If a CID interrupt occurs, user can check FSF to know if this interrupt is caused by FSK modulator. The only way to stop FSK signal immediately is to disable FTE by software. 6 5 4 3 2 Address: C7h 1 (initial=00H) 0 FSKTB.0
6.13 CAS Generator
W925EP01 provides a CAS generator, which outputs the CAS signal to the DTMF pin. The CAS generator can work well at the operating frequency of 4M/8MHz. A CAS generator register CASGE controls the CAS output and specifies the desired low/high frequency. The tones are divided into two groups (low group and high group). When the CASGE is cleared, the DTMF pin is in tri-state. The relation between the CAS signal and the corresponding is shown in following. Bit: 7 CASGE Mnemonic: DTMFG CASGE: Enable CAS tone output to DTMF pin. HE: Enable CAS/DTMF high group frequency output. LE: Enable CAS/DTMF low group frequency output.
HE LE CAS SELECTED TONE
6 DTGE
5 HE
4 LE
3 L1
2 L0 Address: BAh
1 H1
0 H0
0 0 1 1
0 1 0 1
Low 2130Hz 2750Hz 2130Hz & 2750Hz
To change the signal strength of CAS, user can modify the SFR bit0 and bit1 in FSKTC. LO0, LO1: CAS transmitting level option. It just is suitable for 2130Hz. The output levels of 2750Hz will higher 2dBm than it.
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W925EP01/ W925EP01FG
CAS/FSK OUTPUT LEVEL
LO1
LO0
150mV 125mV 100mV 75mV
0 0 1 1
0 1 0 1
6.14 I/O Ports
There are five 8-bits ports named from P0 to P4 in W925EP01. All ports can be configured as input or output mode. Except P0, every port has pull high resistor enable/disable by PxH register. After reset the initial state of each port is in input mode and the value of the registers from P0 to P3 are FFh. The I/O port is described as below: P0: I/O mode is controlled by P0IO. Only P0 output as open drain mode and without pull high resistor. P1: I/O mode is controlled by P1IO. Pull high is controlled by P1H. P1.0~P1.3 work as INT2, P1.4~P1.7 work as INT3. The falling edge on P1 pins will produce INT2 and INT3 flag. P1 is configured as INT2/INT3 by P1EF register. P2: I/O mode is controlled by P2IO. Pull high is controlled by P2H. P3: I/O mode is controlled by P3IO. Pull high is controlled by P3H. P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
RD
Read low pulse signal when reading external RAM Write low pulse signal when writing external RAM Timer/counter 1 external count input Timer/counter 0 external count input External interrupt 1 External interrupt 0 Serial port0 output Serial port0 input
WR
T1 T0
INT1
INT0
TxD RxD
P4: I/O mode is controlled by P4IO. Pull high is controlled by P4H. Special function of P4 is described below. P4.7-5 P4.4 P4.2 P4.1 P4.0 I/O VPOS VNEG SDATA SCLK Normal I/O Positive input of the comparator Negative input of the comparator Serial port1 output Serial port1 input
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W925EP01/ W925EP01FG
6.15 Divider
A built-in 13/14-bit binary up counter designed to generate periodic interrupt. The clock source is from sub-oscillator. When the frequency of sub-crystal is 32768Hz, it provides the divider interrupt in the period of 0.25/0.5 second. Bit DIVS controls the degree of divider. When DIVA is set to high, it will enable the divided counter; when DIVA is low to reset divider and stop counting. As the divider overflows, the divider interrupt flag DIVF is set. DIVF is clear by software or serving divider interrupt routine.
DIVS (CKCON1.1) overflow
D ck CR Q
DIVF
(EXIF.3 )
Fs
DIVA (DIVC.0)
1
1 3
1 4
Executing DIV Int Clear by software
Figure 6-11 13/14-bit Divider
6.16 Timed Access Protection
The W925EP01 has a new feature, CHPCON for ISP function, which are crucial to proper operation of the system. If left unprotected, errant code may write to the CHPCON control bits resulting in incorrect operation and loss of control. In order to prevent this, the W925EP01 has a protection scheme that controls the write access to critical bits. This protection scheme is done using a timed access. In this method, the bits that are to be protected have a timed write enable window. A write is successful only if this window is active, otherwise the write will be discarded. This write enable window is open for 3 machine cycles if certain conditions are met. After 3 machine cycles, this window automatically closes. The window is opened by writing AAh and immediately 55h to the Timed Access(TA) SFR. This SFR is located at address C7h. The suggested code for opening the timed access window is TA REG MOV MOV EEh TA, #AAh TA, #55h ;define new register TA, located at 0EEh
When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the first write (AAh), then the timed access window is opened. It remains open for 3 machine cycles, during which the user may write to the protected bits. Once the window closes the procedure must be repeated to access the other protected bits.
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W925EP01/ W925EP01FG
Examples of Timed Assessing are shown below. Example 1: Valid access MOV TA, #0AAh MOV TA, #055h MOV CHPCON, #I Example 2: Invalid access MOV TA, #0AAh MOV TA, #055h NOP MOV CHPCON, #I Example 3: Invalid access MOV TA, #0AAh NOP MOV TA, #055h MOV CHPCON, #I ;3 M/C ;3 M/C ;3 M/C ;3 M/C ;3 M/C ;1 M/C ;3 M/C ;3 M/C ;1 M/C ;3 M/C ;3 M/C Note: M/C = Machine Cycles
In the first examples, the writing to the protected bits is done before the 3 machine cycle window closes. In Example 2, however, the writing to the protected bit occurs after the window has closed, and so there is effectively no change in the status of the protected bit. In Example 3, the second write to TA occurs 4 machine cycles after the first write, therefore the timed access window in not opened at all, and the write to the protected bit fails.
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
6.17 Hardware Writer Mode
1. H/W Writer Mode This mode is for the writer to write / read Flash EPROM operation. A general user may not enter this mode. 2. Enter Flash Writer Timing
Enter Flash Writer Mode Timing
P3.6 P3.7 P2.6 P2.7 /EA /PSEN RESET Ts = 1us Th =1us X X X X X X
6.18 In-System Programming (ISP) Mode
The W925EP01 equips one 64K byte of main Flash EPROM bank for application program (called APROM) and one 4K byte of auxiliary Flash EPROM bank for loader program (called LDROM). In the normal operation, the micro-controller executes the code in the APROM. If the content of APROM needs to be modified, the W925EP01 allows user to activate the In-System Programming (ISP) mode by setting the CHPCON register. The CHPCON is read-only by default, software must write two specific values AAH, and then 55H sequentially to the TA register to enable the CHPCON write attribute. Writing TA register with the values except AAH and 55H will close CHPCON register write attribute. The W925EP01 achieves all in-system programming operations including enter/exit ISP Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit CHPCON.0 the device will enter in-system programming mode after a wake-up from idle mode. Because device needs proper time to complete the ISP operations before awaken from idle mode, software may use timer interrupt to control the duration for device wake-up from idle mode. To perform ISP operation for revising contents of APROM, software located at APROM setting the CHPCON register then enter idle mode, after awaken from idle mode the device executes the corresponding interrupt service routine in LDROM. Because the device will clear the program counter while switching from APROM to LDROM, the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The device offers a software-reset for switching back to APROM while the content of APROM has been - 68 -
W925EP01/ W925EP01FG
updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software-reset to reset the CPU. The software reset serves as an external reset. This in-system programming feature makes the job easy and efficient in which the application needs to update firmware frequently. In some applications, the in-system programming features make it possible to easily update the system firmware without opening the chassis. NOTE: The ISP Mode operates by supply voltage from 3.3V to 5.5V. SFRAH, SFRAL: The objective address of on-chip Flash EPROM in the in-system programming mode. SFRAH contains the high-order byte of address. SFRAL contains the loworder byte of address. SFRFD: The programming data for on-chip Flash EPROM in programming mode. SFRCN: The control byte of on-chip Flash EPROM programming mode. SFRCN (E7H)
BIT NAME FUNCTION
7
WFWIN
Reserve. On-chip Flash EPROM bank select for in-system programming. = 0: 64K bytes Flash EPROM bank is selected as destination for reprogramming. = 1: 4K bytes Flash EPROM bank is selected as destination for reprogramming. Flash EPROM output enable. Flash EPROM chip enable. The Flash control signals
6
5 4 3, 2, 1, 0
OEN CEN CTRL[3:0]
MODE
WFWIN
OEN
CEN
CTRL<3:0>
SFRAH, SFRAL
SFRFD
Erase 64KB APROM Program 64KB APROM Read 64KB APROM Erase 4KB LDROM Program 4KB LDROM Read 4KB LDROM
0 0 0 1 1 1
1 1 0 1 1 0
0 0 0 0 0 0
0010 0001 0000 0010 0001 0000
X Address in Address in X Address in Address in
X Data in Data out X Data in Data out
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W925EP01/ W925EP01FG
In-System Programming Control Register (CHPCON) CHPCON (EFH)
BIT NAME FUNCTION
7
SWRHWB Set this bit to launch a whole device reset that is same as asserting high to RESET pin, micro-controller will be back to initial state and clear this bit automatically. To read this bit, its alternate function to indicate the ISP hardware reboot mode is invoking when read it in high. LDAP Reserve. This bit is Read Only. High: device is executing the program in LD Flash EPROM. Low: device is executing the program in AP Flash EPROM. Reserve. Reserve. Reserve.
6 5
4 3 2 1 0
-
FBOOTSL Loader program residence selection. Set to high to route the device fetching code from LDROM. FPROGEN In System Programming Mode Enable. Set this bit to launch the ISP mode. Device will operate ISP procedures, such as Erase, Program and Read operations, according to correlative SFRs settings. During ISP mode, device achieves ISP operations by the way of IDLE state. In the other words, device is not indeed in IDLE mode is set bit PCON.1 while ISP is enabled. Clear this bit to disable ISP mode, device get back to normal operation including IDLE state.
F04KBOOT Mode (Hardware Reboot from LDROM) By default, the W925EP01 boots from APROM program after a power on reset. On some occasions, user can force the W925EP01 to boot from the LDROM program via following settings. The possible situation that you need to enter F04KBOOT mode when the APROM program can not run properly and device can not jump back to LDROM to execute in-system programming function. Then you can use this F04KBOOT mode to force the W925EP01 jumps to LDROM and executes in-system programming procedure. When you design your system, you may reserve the pins P4.7 to switches or jumpers. For example in a CD-ROM system, you can connect the P4.7 to PLAY or EJECT buttons on the panel. When the APROM program fails to execute the normal application program, user can press both two buttons (P4.7 & RESET) at the same time and then turn on the power of the personal computer to force the W925EP01 to enter the F04KBOOT mode. After power on of personal computer, you can release both buttons and finish the in-system programming procedure to update the APROM code. In application system design, user must take care of the P2, P3, EA and PSEN pin value at reset to prevent from accidentally activating the programming mode or F04KBOOT mode.
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W925EP01/ W925EP01FG
F04KBOOT MODE
OPTION1 BITS RESET P4.7 MODE
Bit 5 = 0
H
L
REBOOT
The Reset Timing For Entering LD REBOOT Mode(Option1 bit5 = L)
10uS P4.7
20mS Hi-Z
RESET
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
The Algorithm of In-System Programming
Part 1:64KB START
procedure of entering In-System Programming Mode
Enter In-System Programming Mode ? (conditions depend on user's application) Yes
No
Setting control registers MOV TA,#AAH MOV TA,#55H MOV CHPCON,#03H
Execute the normal application program
Setting Timer (about 1.5 us) and enable timer interrupt
END
Start Timer and enter idle Mode. (CPU will be wakened from idle mode by timer interrupt, then enter In-System Programming mode)
CPU will be wakened by interrupt and re-boot from 4KB LDROM to execute the loader program.
Go
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W925EP01/ W925EP01FG
Part 2: 4KB LDROM Go Procedure of the 64KB
Timer Interrupt Service Routine: Stop Timer & disable interrupt PGM
Reset the CHPCON Register: MOV TA,#AAH MOV TA,#55H MOV CHPCON,#03H
End of Programming ?
Yes
No Yes
Setting Timer and enable Timer interrupt for wake-up . (50us for program operation)
Is currently in the F04KBOOT Mode ?
No Software reset CPU and re-boot from the 64KB APROM. MOV TA,#AAH MOV TA,#55H MOV CHPCON,#83H
Get the parameters of new code
Setting Timer and enable Timer interrupt for wake-up . (15 ms for erasing operation) (Address and data bytes) through I/O ports, UART or other interfaces.
Setting erase operation mode: MOV SFRCN,#22H (Erase 64KB APROM)
Setting control registers for programming: MOV SFRAH,#ADDRESS_H MOV SFRAL,#ADDRESS_L MOV SFRFD,#DATA MOV SFRCN,#21H
Start Timer and enter IDLE Mode. (Erasing...)
Hardware Reset to re-boot from new 64 KB APROM. (S/W reset is invalid in F04KBOOT Mode)
End of erase operation. CPU will be wakened by Timer interrupt.
END
Executing new code from address 00H in the 64KB APROM.
PGM
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
Application Note: In-system Programming Software Examples This application note illustrates the in-system programmability of the Winbond W925EP01 Flash EPROM micro-controller. In this example, micro-controller will boot from 64 KB APROM bank and waiting for a key to enter in-system programming mode for re-programming the contents of 64 KB APROM. While entering in-system programming mode, micro-controller executes the loader program in 4KB LDROM bank. The loader program erases the 64 KB APROM then reads the new code data from external SRAM buffer (or through other interfaces) to update the 64KB APROM. ; EXAMPLE 1: ;************************************************************************************************************** ;* Example of 64K APROM program: Program will scan the P1.0. if P1.0 = 0, enters in-system ;* programming mode for updating the content of APROM code else executes the current ROM code. ;* XTAL = 4 MHz ;************************************************************************************************************** .chip 8052 .RAMCHK OFF .symbols CHPCON TA SFRAL SFRAH SFRFD SFRCN EQU EQU EQU EQU EQU EQU ORG LJMP ;* 100H EFH EEH E4H E5H E6H E7H 0H ; JUMP TO MAIN PROGRAM
;************************************************************************ TIMER0 SERVICE VECTOR ORG = 000BH
;********************************************************** **************
ORG CLR MOV MOV TL0,R6 TH0,R7 RETI - 74 00BH TR0 ; TR0 = 0, STOP TIMER0
W925EP01/ W925EP01FG
;************************************************************************ ;* 64K APROM MAIN PROGRAM ORG MAIN_64K: MOV A,P1 ANL A,#01H CJNE A,#01H,PROGRAM_64K PROGRAMMING MODE JMP NORMAL_MODE PROGRAM_64K: MOV TA,#AAH MOV TA,#55H ENABLE MOV CHPCON,#03H PROGRAMMING MODE MOV SFRCN,#00H MOV TCON,#00H MOV IP,#00H MOV IE,#82H FROM IDLE MODE MOV R6,#F0H MOV R7,#FFH MOV TL0,R6 MOV TH0,R7 MOV TMOD,#01H MOV TCON,#10H MOV PCON,#01H SYSTEM ; PROGRAMMING ;******************************************************************************** ;Normal mode 64KB APROM program: depending user's application ;******************************************************************************** ; NORMAL_MODE: ; TMOD = 01H, SET TIMER0 A 16-BIT TIMER ; TCON = 10H, TR0 = 1,GO ; ENTER IDLE MODE FOR LAUNCHING THE IN; CHPCON = 03H, ENTER IN-SYSTEM ; TA = AAH, CHPCON REGISTER WRTE ENABLE ; TA = 55H, CHPCON REGISTER WRITE ; IF P1.0 = 0, ENTER IN-SYSTEM ; SCAN P1.0 100H ;************************************************************************
; SFRCN = 00H ; TR = 0 TIMER0 STOP ; IP = 00H ; TIMER0 INTERRUPT ENABLE FOR WAKE-UP ; TL0 = FEH ; TH0 = FFH
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W925EP01/ W925EP01FG
; ; ; ; ; ; EXAMPLE 2: ;*************************************************************************************************************** ;Example of 4KB LDROM program: This loader program will erase the 64KB APROM first, then reads the new ;code from external SRAM and program them into 64KB APROM bank. XTAL = 4 MHz ;*************************************************************************************************************** .chip 8052 .RAMCHK OFF .symbols CHPCON TA SFRAL SFRAH SFRFD SFRCN EQU EQU EQU EQU EQU EQU ORG LJMP 100H EFH EEH E4H E5H E6H E7H 000H ; JUMP TO MAIN PROGRAM . . . . . ; User's application program
;************************************************************************ ;* 1. TIMER0 SERVICE VECTOR ORG = 0BH ;************************************************************************ ORG 000BH CLR TR0 MOV TL0,R6 MOV TH0,R7 RETI ;************************************************************************ ;* 4KB LDROM MAIN PROGRAM ORG 100H - 76 ;************************************************************************ ; TR0 = 0, STOP TIMER0
W925EP01/ W925EP01FG
MAIN_4K: MOV R4,#03H MOV TA,#AAH MOV TA,#55H MOV CHPCON,#03H PROGRAMMING. MOV SFRCN,#00H MOV TA,#00H MOV TCON,#00H MOV TMOD,#01H MOV IP,#00H MOV IE,#82H MOV R6,#F0H MOV R7,#FFH MOV TL0,R6 MOV TH0,R7 MOV TCON,#10H MOV PCON,#01H UPDATE_64K: MOV TCON,#00H MOV IP,#00H MOV IE,#82H MOV TMOD,#01H MOV R6,#D0H 15 mS. DEPENDING MOV R7,#8AH MOV TL0,R6 MOV TH0,R7 ERASE_P_4K: MOV SFRCN,#22H MOV TCON,#10H ; SFRCN(E7H) = 22H ERASE 64K ; TCON = 10H, TR0 = 1,GO ; TCON = 00H , TR = 0 TIM0 STOP ; IP = 00H ; IE = 82H, TIMER0 INTERRUPT ENABLED ; TMOD = 01H, MODE1 ; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT ; ON USER'S SYSTEM CLOCK RATE. ; TCON = 10H, TR0 = 1, GO ; ENTER IDLE MODE ; DISABLE TA WRITE ATTRIBUTE ; TCON = 00H, TR = 0 TIMER0 STOP ; TMOD = 01H, SET TIMER0 A 16BIT TIMER ; IP = 00H ; IE = 82H, TIMER0 INTERRUPT ENABLED ; ERROR COUNTER ; TA = AAH, CHPCON WRITE ENABLE. ; TA = 55H, CHPCON WRITE ENABLE. ; CHPCON = 03H, ENABLE IN-SYSTEM
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
MOV PCON,#01H ; ENTER IDLE MODE (FOR ERASE OPERATION)
;********************************************************************* ;* BLANK CHECK ;********************************************************************* MOV SFRCN,#0H MOV SFRAH,#0H MOV SFRAL,#0H MOV R6,#FDH MOV R7,#FFH MOV TL0,R6 MOV TH0,R7 BLANK_CHECK_LOOP: SETB TR0 MOV PCON,#01H MOV A,SFRFD INC SFRAL MOV A,SFRAL JNZ BLANK_CHECK_LOOP INC SFRAH MOV A,SFRAH CJNE A,#0H,BLANK_CHECK_LOOP JMP PROGRAM_64KROM BLANK_CHECK_ERROR: MOV P1,#F0H MOV P3,#F0H JMP $ ;******************************************************************************* ;RE-PROGRAMMING 64KB APROM BANK ;******************************************************************************* PROGRAM_64KROM: MOV R2,#00H MOV R1,#00H - 78 ; TARGET LOW BYTE ADDRESS ; TARGET HIGH BYTE ADDRESS ; END ADDRESS = FFFFH ; ENABLE TIMER 0 ; ENTER IDLE MODE ; READ ONE BYTE ; NEXT ADDRESS ; SET TIMER FOR READ OPERATION, ABOUT 1.5 mS. ; READ 64KB APROM MODE ; START ADDRESS = 0H
CJNE A,#FFH,BLANK_CHECK_ERROR
W925EP01/ W925EP01FG
MOV DPTR,#0H MOV SFRAH,R1 MOV SFRCN,#21H MOV R6,#9CH ABOUT 50 mS. MOV R7,#FFH MOV TL0,R6 MOV TH0,R7 PROG_D_64K: MOV SFRAL,R2 ; SFRAL(E4H) = LOW BYTE ADDRESS ; THIS FUNCTION CALL IS BASE DATA TO EXTERNAL SRAM CALL GET_BYTE_FROM_PC_TO_ACC ON USER'S CIRCUIT MOVX @DPTR,A BUFFER MOV SFRFD,A MOV TCON,#10H MOV PCON,#01H INC DPTR INC R2 CJNE R2,#0H,PROG_D_64K INC R1 MOV SFRAH,R1 CJNE R1,#0H,PROG_D_64K ;***************************************************************************** ; * VERIFY 64KB APROM BANK ;***************************************************************************** MOV R6,#FDH MOV R7,#FFH MOV TL0,R6 MOV TH0,R7 MOV DPTR,#0H MOV R2,#0H MOV R1,#0H MOV SFRAH,R1 MOV SFRCN,#00H ; Target ; Target ; The start address of sample code low byte address high byte address ; SET TIMER FOR READ VERIFY, ABOUT 1.5 mS. ; SFRFD(E6H) = DATA IN ; TCON = 10H, TR0 = 1,GO ; ENTER IDLE MODE (PRORGAMMING) ;SAVE ; EXTERNAL SRAM BUFFER ADDRESS ; SFRAH, TARGET ; SET TIMER HIGH ADDRESS FOR PROGRAMMING, ; SFRCN(C7H) = 21 (PROGRAM 64K)
; SFRAH, Target high address ; SFRCN = 00 (Read ROM CODE) Publication Release Date: Apr. 10, 2006 Revision A2
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W925EP01/ W925EP01FG
READ_VERIFY_64K: MOV SFRAL,R2 MOV TCON,#10H MOV PCON,#01H INC R2 MOVX A,@DPTR INC DPTR CJNE A,SFRFD,ERROR_64K CJNE R2,#0H,READ_VERIFY_64K INC R1 MOV SFRAH,R1 CJNE R1,#0H,READ_VERIFY_64K ;****************************************************************************** ;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU ;****************************************************************************** MOV TA,#AAH MOV TA,#55H MOV CHPCON,#83H ERROR_64K: DJNZ R4, UPDATE_64K . PROCESS TO DEAL WITH IT. . ; IF ERROR OCCURS, REPEAT 3 TIMES. ; IN-SYSTEM PROGRAMMING FAIL, USER'S ; TA = AAH ; TA = 55H ; CHPCON = 83H, SOFTWARE RESET. ; SFRAL(E4H) = LOW ADDRESS ; TCON = 10H, TR0 = 1,GO
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W925EP01/ W925EP01FG
6.19 Security Bits
Using device programmer, the Flash EPROM can be programmed and verified repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected. The protection of Flash EPROM and those operations on it are described below. The W925EP01 has Special Setting Register, which can be accessed by device programmer. The register can only be accessed from the Flash EPROM operation mode. Those bits of the Security Registers cannot be changed once they have been programmed from high to low. They can only be reset through erase-all operation.
D7 D6 D5 D4 D3 D2 D1 D0 11011010 01100010
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
Company ID (#DAH) Device ID (#D4H) Option0 Bits Option1 Bits
4KB Flash EPROM Program Memory LDROM
0000h
0FFFh 64KB Flash EPROM Program Memory APROM
Option0 Bits
B1: High/Low speed for EEPROM acess, logic 0: Low speed logic 1: High speed B2: 4MHz/8MHz selection, logic 0: 8MHz logic 1: 4MHz B4: Encryption(Scramble) & Lock bit logic 0: the encryption logic & lock enable logic 1: the encryption logic & lock disable B5: H/W Reboot path logic 0: enable reboot by P4.7 logic 1: disable reboot by P4.7
Reserved Reserved
Option Registers
FFFFh
Special Setting Registers
Default 1 for all security bits. Reserved bits must be kept in logic 1.
Option1 Bits
B2: Sub crystal oscillator starting counter logic 0: 10 level logic 1: 16 level B4: Main crystal oscillator starting counter logic 0: 16 level logic 1: 12 level
Option0: B1: High/Low speed for EEPROM access B2: 4M/8MHz oscillator selection If this bit is set to logic 0, the oscillator will operate at 8MHz. If this bit is set to logic 1, the oscillator will operate at 4MHz. B4: Encryption(Scramble) & Lock bit This bit is used to protect the customer's program code. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the Flash EPROM data and Special Setting Registers cannot be accessed again. Publication Release Date: Apr. 10, 2006 Revision A2
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W925EP01/ W925EP01FG
This bit is also used to enable/disable the encryption logic for code protection. Once encryption feature is enabled, the data presented on Data0~7 will be encoded via encryption logic. Only whole chip erase will reset this bit. B5: P4.7 H/W Reboot function If this bit is set to logic 0, it will enable P4.7 to reboot. Option1: B2: Sub Crystal Oscillator Starting Counter If this bit is set to logic 0, it will delay 10 levels from crystal starting.
IF THIS BIT IS SET TO LOGIC 1, IT WILL DELAY 16 LEVELS FROM CRYSTAL STARTING.
B4: Main Crystal Oscillator Starting Counter If this bit is set to logic 0, it will delay 16 levels from crystal starting.
IF THIS BIT IS SET TO LOGIC 1, IT WILL DELAY 12 LEVELS FROM CRYSTAL STARTING.
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W925EP01/ W925EP01FG
6.20 Calling Identity Delivery (CID)
W925EP01 provides type I and type II of CID system. Type I is on-hook calling with CID message and type II is off-hook call on waiting. The CID function includes FSK decoder, dual tone alert signal detector, ring detector and DTMF receiver. The FSK demodulation function can demodulate Bell 202 and ITU-T V.23 Frequency Shift keying (FSK) with 1200-baud rate. The Tone Alert Signal detect function can detect dual tones of Bellcore Customer Premises Equipment(CPE) Tone Alerting Signal(CAS) and BT Idle State and Loop State Tone Alert Signal. The line reversal for BT, ring burst for CCA or ring signal for Bellcore can be detected by ring detector. It is compatible with Bellcore TRNWT-000030 & ST-TSV-002476, British Telecom(BT) SIN227, U.K. Cable Communications Association(CCA) specification. The DTMF receiver can be programmed as DTMF decoder to decode 16 DTMF signals or tone detector to detect the signal which frequency is in DTMF band. The tone detector can be an auxiliary detector to improve the performance of detecting tone-alerting signal(CAS), said as talk down-off, in type II system. The FSK decoder, alert tone detector and DTMF receiver can be enable/disable individually by the bits of FSKE, CASE and DTMFE in FSK DATA REGISTER(FSKDR). CIDE is the global control bit to enable/disable FSK decoder, alert tone detector and DTMF receiver. However, the ring detector is always active.
CIDGD CIDGA DTMFE
PGD <7:4>
High Tone Bandpass Filter PHAD<3:0>
High Tone Detector Low Tone Detector
INP2 INN2 GCFB2
Input Pre-processor + -
Guard Time Timer
ESt Decode data and Latch
PGAF <3:0>
Anti-alias Filter
PGD <3:0>
Low Tone Bandpass Filter
DTMFD
DD3-DD0
FSKE
DTMFPT/DTMFAT
FDATA
FSK Demodulation Circuit
FSK Bandpass Filter
Input Pre-processor
FSK Demodulator
PHFL<7:4>
FSK Data Output Interface
INP1 INN1 GCFB1 VREF CAP CIDE,RST VADD VASS
+ -
PGAF <7:4>
FD7-FD0 FDR FCD
Anti-alias Filter
FSK Carrier Detector
CASE
To internal circuit Bias Voltage Generator
High Tone Bandpass Filter PHAD<7:4> Low Tone Bandpass Filter
PHFL<3:0>
Dual Tone Alert Signal Detection Circuit High Tone Detector Low Tone Detector Guard Time Circuit
Interrupt Generator
ALGO CASPT/CASAT
Clock Driver To internal circuit
Ring Detector
RNG
Fm
RNGDI
RNGRC
PS: The signals noted in italic and underline type are CID pins on the chip.
Figure 6-12 The CID Block Diagram
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
Ring Detector The application circuit in Figure 6-13 illustrates the relationship between the RNGDI, RNGRC and RNG signals. The combination of RNGDI and RNGRC is used to detect an increase of the RNGDI voltage from ground to a level above the Schmitt trigger high going threshold voltage VT+.
C1=0.1uF Tip/A R3=200K RNGDI R1=470K
C1=0.1uF Ring/B R2=470K
R4=300K
R5=150K RNGRC RNG
C3=0.22uF
Allowance minimal ring voltage (peak to peak) is: Vpp (max ring) = 2 (VT+(max) (R1 + R3 + R4) / R4 + 0.7) Tolerance to noise between Tip and Ring and VSS is: Vpeak (max noise) = VT+(min) (R1 + R3 + R4) / R4 + 0.7 Time constant is: T = R5 C3 ln [VDD / (VDD - VT+)] VT+(min) <= VT+ <= VT+(max) R5 from 10K ohm to 500K ohm. C3 from 47 nF to 0.68 uF.
Figure 6-13 Application Circuit of the Ring Detector
The RC time constant of the RNGRC pin is used to delayed the output pulse of the RNG flag for a low going edge on RNGDI. This edge goes from above the VT+ voltage to the Schmitt trigger low going threshold voltage VT-. The RC time constant must be greater than the maximum period of the ring signal, to ensure a minimum RNG high interval and to filter the ring signal to get an envelope output. The rising signal of RNG will set the bit RNGF(CIDFG.0) high to cause the CID flag(CIDF) high. The diode bridge shown in Figure 6-13 works for both single ended ring signal and balanced ringing. The R1 and R2 are used to set the maximum loading and must be of equal value to achieve balanced loading at both the tip and ring line. R1, R3 and R4 form a resistor divider to supply a reduced voltage to the RNGDI input. The attenuation value is determined by the detection of minimal ring voltage and maximum noise tolerance between tip/ring and ground.
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W925EP01/ W925EP01FG
Input Pre-Processor The input signal is processed by Input Pre-Processor, which is comprised of two OP amps and a bias source(VREF). The gain OP-amps are used to bias the input voltage with the VREF signal voltage. VREF is VAD/2 typically, this pin is recommended to connect a 0.1uF capacitor to VAS. The gain adjustable OP amps are sued to select the input gain by connecting a feedback resistor between GCFB and INN pins. Figure 6-14 shows the differential input configuration and Figure 6-15 shows the single-ended configuration.
C1
R3 R1
R4
0.1uF
VREF
INP INN
+ -
C2
R2
R5
GCFB
Voltage Gain Av = R5 / R1 Input Impedance 2 2 Zin = 2 R1 + (1 / wC)
Differential Input Amplifier C1 = C2 R1 = R2 R3 = (R4 R5) / (R4 + R5)
Figure 6-14 Differential Input Gain Control Circuit
0.1uF
VREF
C 22n
INP
R1 R2
+ -
INN
GCFB
Voltage Gain Av = R2 / R1
Figure 6-15 Single-Ended Input Gain Control Circuit
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
CAS/DTAS Detection In off-hook services (type II), the detection of CAS/DTAS will affect the quality of the call waiting service. When the CAS/DTAS is sent from far end, sometimes the near end user maybe still talking. The CPE must be able to detect the CAS/DTAS successfully in the presence of near end speech. To detect CAS/DTAS from telephone hybrid receiver pair improves the detection. However, in BT's onhook CID system the CAS/DTAS detection is from Tip/Ring pair. The dual tone alert signal is separated into high and low tones and detected by a high/low tone detector. When the alert tone is recognized by the detector, the bit ALGO will go high and the rising signal will set the bit ALGOF in CIDFG to produce the CID flag(CIDF). Figure 6-16 shows the guard time waveform of detecting alert tone. The total recognition time is tREC=tDP+tGP, where tDP is the tone present detect time and tGP is the tone present guard time. The total absent guard time is tABS=tDA+tGA where tDA is the tone absent detect time and tGA is the tone absent guard time. The tone present/absent guard time is determined by guard-time timer, which the input clock period is 0.858mS. When the alert tone is detected, the internal signal ALGR will be set and the rising edge of ALGR resets the guard-time timer and the timer starts up counting from 00H. As the content of the timer is the same as the register CASPT, the timer stops counting and the bit ALGO will be set and the rising edge of ALGO triggers the flag ALGOF to become high. The counting of tone absent time is similar to the counting of tone present time but the falling edge of ALGR/ ALGO replaces the rising edge and the CASAT replaces the CASPT. The bit ALGO is controlled by hardware only. The flag ALGOF is set by rising edge of ALGO and cleared by software.
Vin
t DP Dual Alert Tone Signal t DA t DP t DA
ALGR *
t GP t GA
ALGO
+
ALGOF
t REC
tABS
1
3
2
3
1
1: Guard time timer is reset and starts to up count from 00H. 2: Guard time timer is reset and starts to up count from 00H. 3: The content of the guard-time timer reaches the content of ASPT/ASAT.
*ALGR is an internal signal in the uC. + Clear by software.
Figure 6-16 Guard Time Waveform of Alert Tone Signal Detection
DTMF Decoder The DTMF decoder shares the same input pre-processor with FSK decoder. The dual tone is separated into low group and high group by two SCFs (switched capacitor filter. The method of DTMF detection is the same as alert tone detection. The present/absent guard time can adjust by registers DTMFPT/DTMFAT. As the DTMF signal is recognized and decoded, the bit DTMFD will be set and the decoded DTMF data is stored in bit0 to bit3 of register DTMFDR. The rising edge of DTMFD produces the flag DTMFDF. The bit DTMFD is controlled by hardware only. The flag DTMFDF is set by rising edge of DTMFD and cleared by software.
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W925EP01/ W925EP01FG
Vin (Tip/ring)
t DP
TONE #n t DA
ESt *
t REC
t GP t GA t ABS
DTMFD DTMFDF
+
DTMFDR
Tone #n-1 1 3
Tone #n 2 3
1: Guard time timer is reset and starts to up count from 00H. 2: Guard time timer is reset and starts to up count from 00H. 3: The content of the up counting timer reaches the register DTMFPT/DTMFAT.
* ESt is an internal signal in the circuit. + Clear by software. Figure 6-17 The Waveform of DTMF Detection
Tone Detector In off-hook state, said type II system, detecting tone alert signal (CAS) is easily interfered by human's voice or other noise in voice band. Sometimes the interference makes falsely recognizing a noise as a CAS (talk-off), or lost detecting a real CAS (talk-down). The DTMF can be programmed as a tone detector by setting bit 4 of DTMFR2. The frequency band of the tone detector is DTMF frequency from 697Hz to 1633Hz. Once the tone detector gets signals in the band, the bit of DTMFH or DTMFL in register DTMFDR will become high immediately. User can poll these 2 bits to check if the tone exists on the tip/ring. The input gain of tone detector is the same as DTMF receiver. FSK Decoder The FSK carrier detector provides an indication of the present of a signal within the FSK frequency band. If the output amplitude of the FSK band-pass filter is sufficient to be detected continuously for 8 mS, the FSK carrier detected bit FCD will go high and it will be released if the FSK band-pass filter output amplitude is not able to be detected for greater than 8 mS. The 8 mS is the hysteresis of the FSK carrier detector. Figure 6-18 shows the timing of FSK carrier detection.
Tip/Ring t FSKE FSKE FCD
Note
Analog FSK Signal
Analog FSK Signal
t CA t CP
t CP t CA
Figure 6-18 FSK Detection Enable and FSK Carrier Present and Absent Timing
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
The FSK demodulation function can demodulate Bell 202 and ITU-T V.23 Frequency Shift keying (FSK) with 1200-baud rate. When the decoder receives the FSK serial data, the serial data will be demodulated into bit FDATA with 1200-baud rate in the mean time the synchronous clock signal is output to the bit FCLK. As the decoder receives one byte, the internal serial-to-parallel circuit sets the bit FDR and converts the 8-bit serial data into the byte register FSKDR. The rising edge of bit FDR will set the flag FDRF to produce CID interrupt but FDRF is cleared by software. User can get the FSK data by reading register FSKDR or sampling the bit FDATA. The timing of FSK demodulation is shown in Figure 6-19.
start
1st byte data b0 b1 b2 b3 b4 b5 b6 b7 1* t IDD 1st byte data b0 b1 b2 b3 b4 b5 b6 b7
stop 1
start 0
2nd byte data
stop start 0 b0
Tip/Ring
1*
1
0
b0 b1 b2 b3 b4 b5 b6 b7 1
start
stop
start
2nd byte data b0 b1 b2 b3 b4 b5 b6 b7
stop start
FDATA
1/fDCLK0
FCLK
tCRD t RH
FDR FDRF FSKDR * Mark bit or redundant stop bit(s), will be omitted. + Clear by software.
1st byte data
+
2nd byte data
Figure 6-19 Serial Data Interface Timing of FSK Demodulation
CID Input Gain Control The CID input gain and input hysteresis are controllable by internal CID gain control registers. CIDGD and CIDGA registers determine the 6 internal CID gain control registers. CID gain control data register (CIDGD) presents the data bus. The lower 3 bits of CID gain control address register (CIDGA) present the address. The rising edge of CIDGA.4 will latch the CIDGD in the corresponding internal CID gain control register. The 6 internal CID gain control registers are addressed as following table. Setting the 6 registers as the suggestion value guarantees the CID spec.
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W925EP01/ W925EP01FG
ADDRESS (CIDGA.2-0)
INTERNAL CID GAIN CONTROL REGISTER
SUGGESTION VALUE
000 001 002 003 004 005
DTMFR1: DTMF register1 DTMFR2: DTMF register2 PGAF: Programmable gain control alert tone and FSK PGAD: Programmable gain control DTMF PHAD: Programmable hysteresis alert tone and DTMF PHFL: Programmable hysteresis FSK and low pass filter
0000 0001B 011X 0001B 99H A7H 35H 33H
X=0 DTMF receiver works a DTMF decoder, X=1 DTMF receiver works as a tone detector.
The signals to set internal CID gain control registers is shown in Figure 6-20
CIDGA CIDGA<2:0>
CIDGD
CIDGD
CIDGA.3
Rising latch
Figure 6-20 Internal CID Gain Control Register Setting Waveform
DTMFR1 DTMFR1 [7:4] are reserved bits and must be 0000b.
BIT3~BIT0 ACCEPTABLE ERROR PERCENTAGE TO SAMPLE 4 PERIOD OF ROW FREQ.
0000 0001 001X 01XX 1XXX DTMFR2
BIT3~BIT0
0.6% (default) 2.5% 3.5% Reserved Reserved
ACCEPTABLE ERROR PERCENTAGE TO SAMPLE 4 PERIOD OF COL FREQ.
0000 0001 001X 01XX 1XXX
0.5% (default) 1.5% 2.5% Reserved Reserved
The acceptable error percentage may have small variation by different test environments.
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
DTMFR2.4=0 DTMFR2.4=1 DTMFR2.5=0 DTMFR2.5=1 DTMFR2.6=0 DTMFR2.6=1
DTMF receiver works as a DTMF receiver DTMF receiver works as a tone detector DTMF PT counter is up counter type, detected frequency changed does not effect counter DTMF PT counter is up counter type, detected frequency changed resets DTMF PT counter DTMF AT counter is up-down counter type, up counting when no DTMF detected, down counting if DTMF detected again. DTMF AT counter is up counter type, up counting when no DTMF detected, pause counting if DTMF detected again.
DTMFR2.7: reserved There are 4 programmable gain arrays, shown in Figure 6-12, are determined by Low/High nibbles of PGxx. The following table lists the input gain corresponding to the value of L/H nibble of PGxx.
X 20 LOG((40+15*X)/(230-(40+15*X))) DB X 20 LOG((40+15*X)/(230-(40+15*X))) DB
0 1 2 3 4 5
-13.53 -10.05 -7.18 -4.64 -2.28 0.00
6 7 8 9 10
2.28 4.64 7.18 10.05 13.53 X is the value of L/H nibble of PGxx
There are 4 programmable hysteresis input buffer, shown in Figure 6-12, are determined by Low/ High nibbles of PHxx. The hysteresis control formulas are list below. Alert tone hysteresis DTMF hysteresis FSK hysteresis FSK detector hysteresis HAT=13mv + 3mv*X HDTMF=6mv + 3mv*X HFSK=13mv + 3mv*X HFSKD=13mv + 3mv*X X=PHAD<7:4> X=PHAD<3:0> X=PHFL<7:4> X=PHFL<3:0>
Application Circuit The analog interface circuit of W925EP01 shown in Figure 6-21 is a typical CPE system. The gain control op-amp is set to unit gain to allow the electrical characteristics to be met in this application circuit.
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W925EP01/ W925EP01FG
Tip/A
22nF
430K
34K
INP2 INN2 Ring/B
22nF 430K 34K 53K6 464K 60K4 0.1uF 0.1uF 470K 150K
GCFB2 VREF CAP RNGDI
200K 0.1uF 470K 464K Microphone Tip Ring 464K 22nF Tx+ TxRx+ RxSpeaker 100K 60K4
RNGRC
0.47u
60K4
INP1 INN1
Speech Network
464K 22nF
464K
GCFB1
Resistor must have 1% tolerance Resistor must have 5% tolerance
Figure 6-21 Application Circuit of CID
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
Application Environment There are three major timing differences for CID sequences, Bellcore, BT and CCA. Figure 6-22 is the timing diagram for Bellcore on-hook data transmission and Figure 6-23 is the timing diagram for the Bellcore off-hook data transmission. Figure 6-24 is the timing diagram for the BT caller display service on-hook data transmission and Figure 6-25 is the timing diagram for the BT caller display service offhook data transmission. Figure 6-26 is the timing diagram for the CCA caller display service for onhook data transmission. The CID flag (CIDF) must be cleared by software when each time the CID interrupt routine is serviced. The CID global enable signal (CIDE) must be set high.
Tip/Ring
1st Ring A B
Ch. seizure C ...
Mark D
Message E ... F
2nd Ring
CIDF
RNG
FSKE
FCD
FDR
...
...
FCLK
FDATA
...101010...
Data
A = 2 sec typical B = 250-500mS C = 250mS D = 150mS E = depend on data length MAX C+D+E = 2.9 TO 3.7 sec F >= 200mS
Figure 6-22 Input and Output Timing of Bellcore On-hook Data Transmission
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W925EP01/ W925EP01FG
CPE goes off-hook
CPE mutes handset & disables keypad CPE sends
CPE unmutes handset and enable keypad
Tip/Ring
CAS A B
ACK C D
Mark E
Message F G
ASE
CIDF t REC t ABS
...
ALGO
FSKE
FCD
FDR
...
FCLK
FDATA
Data
A = 75 - 85mS B = 0 - 100mS C = 55 - 65mS D = 0 - 500mS E = 58 - 75mS F = depends on data length G <= 50mS
Figure 6-23 Input and Output Timing of Bellcore Off-hook Data Transmission
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
Line Reversal
A/B Wires A
Alert Signal B C
Ch. Seizure D
Mark E
Message F G
Ring
RNGON
ASE
CIDF t ABS
...
...
ALGO
t REC
TE DC load
< 120uA
15
1 ms < 0.5 mA (optiona) Current wetting pulse (Refer to SIN227)
50 - 150 ms
TE AC load
20
5 ms
Note 1
Zss (Refer to SIN227)
Note 2
FSKE
Note 3
FCDN
FDRN
...
...
DCLK
DATA
...101010...
Data
A >= 100mS B = 88 - 100mS C >= 45mS (up to 5Sec) D = 80 - 262mS E = 45 - 75mS F <= 2.5S (500mS typical) G >= 200mS
Figure 6-24 Input and Output Timing of BT Idle State (On-hook) Data Transmission Note: 1. SIN227 specifies that the AC and DC loads should be applied at 20 5mS after the end of the dual tone alert signal. 2. SIN227 specifies that the AC and DC loads should be removed between 50 - 150mS after the end of the FSK signal. 3. The FSKE bit should be set low to disable the FSK decoder when FSK is not expected. The tone alerting signal speech and the DTMF tones are in the same frequency band as the FSK signal.
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W925EP01/ W925EP01FG
CPE goes off-hook Start Point Tip/Ring Note 1 A Note 3 CAS B
CPE mutes handset & disables keypad CPE sends ACK C D E Mark F Message G
CPE unmutes handset and enable keypad
H
ASE
CIDF t REC t ABS
...
ALGO
FSKE
Note 2
Note 4
Note 5
FCD
FDR
...
FCLK
FDATA
Data
A = 40 - 50mS B = 80 - 85mS C <= 100mS D = 65 - 75mS E = 5 - 100mS F = 40 - 75mS G = depends on data length H <= 100mS
Figure 6-25 Input and Output Timing of BT Loop State (Off-hook) Data Transmission Note: 1. In a CPE where AC power is not available, the designer may choose to switch over to line power when the CPE goes off-hook and use battery power while on-hook. 2. The FSKE bit may be set low to prevent the alert tone, speech or other FSK in-band noise decoded by FSK demodulator and give false data when the dual tone alert signal is expected. If the FSKE pin cannot controlled by microcontroller, the FSKE bit must always placed in high state and the micro controller must give up the FSK decoded data when the FSK signal is not expected. 3. The exchange will have already disabled the speech path to the distant customer in both transmission directions. 4. The FSKE should be set high as soon as the CPE has finished sending the acknowledge signal ACK. 5. The FSKE may be set low after the last byte (check sum) has been decoded or FCD has become inactive. 6. In an unsuccessful attempts where the exchange does not send the FSK signal, the CPE should disable FSKE, un-mute the handset and enable the keypad after this interval.
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
Line Reversal A/B Wires Ring Burst A B Ch. Seizure C Mark D Message E F
First Ring Cycle
RNG
CIDE
Note 4
CIDF
...
... 50 - 150 ms
TE DC load
250 - 400 ms
TE AC load
Note 2
Note 3
FSKE
Note 1
FCD
FDR
...
...
FCLK
FDATA
...101010...
Data
A = 200 - 450mS B >= 500mS C = 80 - 262mS D = 45 - 262mS E <= 2.5sec (500ms typical) F >= 200mS
Figure 6-26 Input and Output Timing of CCA Caller Display Service Data Transmission Notes: 1. The CPE designer may choose to set FSKE always high while the CPE is on-hook and the FSK signal is expected. 2. TW/P & E/312 specifies that the AC and DC loads should be applied between 250 - 400 mS after the end of the ring burst. 3. TW/P & E/312 specifies that the AC and DC loads should be removed between 50 - 150 ms after the end of the FSK signal. 4. The CID may not be enable up at the first ring cycle after the FSK data had been processed.
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W925EP01/ W925EP01FG
7. TIMING WAVEFORMS
Program Fetch Cycle(Two Machine Cycle)
Instruction Fetch C1 CLK PSEN D7-D0 A16-A0
OP-CODE
Address A16-A0
Operand Fetch C4 C1 C2 C3 C4
C2
C3
OPERAND
Address A16-A0
Data Read Cycle
Last Cycle of Previous Instruction
First Machine cycle
Second Machine cycle
Next Instruction Machine Cycle
MOVX instruction cycle
C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK PSEN RD D7-D0
MOVX Inst. Address MOVX Inst.
D7-D0 D7-D0 D7-D0 D7-D0
Next Inst. Address
MOVX Data Address MOVX Data in A16-A0 A16-A0
Next Inst. Read
A16-A0
A16-A0
A16-A0
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
Timing Waveforms, continued
Data Write Cycle
Last Cycle of Previous Instruction
First Machine cycle
Second Machine cycle
Next Instruction Machine Cycle
MOVX instruction cycle
C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK PSEN WR D7-D0
MOVX Inst. Address MOVX Inst.
D7-D0 D7-D0 D7-D0 D7-D0
Next Inst. Address
MOVX Data Address MOVX Data out A16-A0 A16-A0
Next Inst. Read
A16-A0
A16-A0
A16-A0
7.1
Instruction Timing
The instruction timing for the W925EP01 is an important aspect, especially for those users who wish to use software instructions to generate timing delays. Also, it provides the user with an insight into the timing differences between the W925EP01 and the standard 8032. In the W925EP01 each machine cycle is four clock periods long. Each clock period is designated a state. Thus each machine cycle is made up of four states, C1, C2 C3 and C4, in that order. Due to the reduced time for each instruction execution, both the clock edges are used for internal timing. Hence it is important that the duty cycle of the clock be as close to 50% as possible to avoid timing conflicts. As mentioned earlier, the W925EP01 does one op-code fetch per machine cycle. Therefore, in most of the instructions, the number of machine cycles needed to execute the instruction is equal to the number of bytes in the instruction. Of the 256 available op-codes, 128 of them are single cycle instructions. Thus more than half of all op-codes in the W925EP01 are executed in just four clock periods. Most of the two-cycle instructions are those that have two byte instruction codes. However there are some instructions that have only one byte instruction, yet they are two cycle instructions. One-instruction which is of importance is the MOVX instruction. In the standard 8032, the MOVX instruction is always two machine cycles long. However in the W925EP01, each machine cycle is made of only 4 clock periods compared to the 12 clock periods for the standard 8032. Therefore, even though the number of categories has increased, each instruction is at least 1.5 to 3 times faster than the standard 8032 in terms of clock periods.
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W925EP01/ W925EP01FG
Single Cycle C1 CLK PSEN D7-D0 A16-A0
Data D7-0
C2
C3
C4
Address A16-A0
Single Cycle Instruction Timing
Instruction Fetch C1 CLK PSEN D7-D0 A16-A0
D7-D0
Address A16-A0
Operand Fetch C4 C1 C2 C3 C4
C2
C3
D7-D0
Address A16-A0
Two Cycle Instruction Timing
Instruction Fetch C1 CLK PSEN D7-D0 A16-A0 OP-CODE Address A16-A0 C2 C3 C4 C1
Operand Fetch C2 C3 C4 C1
Operand Fetch C2 C3 C4
OPERAND Address A16-A0
OPERAND Address A16-A0
Three Cycle Instruction Timing
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
Instruction Fetch C1 CLK PSEN D7-D0
OP-CODE
Operand Fetch C1 C2 C3 C4
Operand Fetch C1 C2 C3 C4
Operand Fetch C1 C2 C3 C4
C2
C3
C4
OPERAND
OPERAND
OPERAND
A16-A0
Address A16-A0
Address A16-A0
Address A16-A0
Address A16-A0
Four Cycle Instruction Timing
Instruction Fetch
C1 C2 C3 C4
Operand Fetch
C1 C2 C3 C4
Operand Fetch
C1 C2 C3 C4
Operand Fetch
C1 C2 C3 C4
Operand Fetch
C1 C2 C3 C4
CLK PSEN D7-D0
OP-CODE OPERAND OPERAND OPERAND OPERAND
A16-A0
Address A16-A0
Address A16-A0
Address A16-A0
Address A16-A0
Address A16-A0
Five Cycle Instruction Timing
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W925EP01/ W925EP01FG
8. ELECTRICAL CHARACTERISTICS
8.1 Maximum Ratings*
PARAMETER SYMBOL RATING UNITS
(Voltage referenced to VSS pin)
1 2 3 4
Supply Voltage with respect to VSS Voltage on any pin other than supplies (note 1) Current at any pin other than supplies Storage Temperature
VDD
-0.3 to 6 -0.7 to VDD + 0.7 0 to 10
V V mA
Tst
-65 to 150
Note: *. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the lift and reliability of the device. 1. VDD + 0.7 should not excess maximum rating of supply voltage.
8.2
Recommended Operating Conditions
CHARACTERISTICS SYMBOL RATING UNIT
Power Supplies (Analog) Power Supplies (Digital) Flash EPROM type THE ISP MODE OPERATES Main Clock Frequency Sub Clock Frequency Tolerance on Clock Frequency Operation Temperature
VAD VDD VDD fOSC fSUB
3.0 to 6.0 2.4 to 5.5 3.3 to 5.5 4/8 32768 -0.1 to +0.1 0 to 75
V V V MHz Hz % C
fC
Top
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
8.3 DC Electrical Characteristics
PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT NOTE
(VDD-VSS=3.0V, Fm=4MHz at non-specified note, Ta=25C, all output unloaded & input fixed state)
IOP1 IOP2 IOP3 Operating Current IOP4 IOP5 IOP6 I/O Ports Input High Voltage I/O Ports Input Low Voltage I/O Ports Output High Voltage I/O Ports Output Low Voltage BUZ Pin Output High Voltage BUZ Pin Output High Voltage DTMF Output DC Level DTMF Distortion DTMF Output Voltage Pre-emphasis FSK Output DC Level VFDC VIH VIL VOH VOL VBOH VBOL VTDC DTHD VTO
FSK On, dual clock, normal run FSK Off, dual clock, normal run FSK off, slow run, main osc stopped Idle mode, dual clock Idle mode, main osc stopped Power down mode 0.7VDD VSS IOH = 2.0mA IOL = 2.0mA IOH = 3.5mA IOL = 3.5mA RL = 5K, VDD = 2.5-3.8 RL = 5K, VDD = 2.5-3.8 Low group, RL = 5K Col/Row RL = 5K, VDD = 2.5-3.8 2.4 2.4 0.4 1.1 130 1 1.1
2.8 4.8 1.8 3.8 20 730 1.0 2.0 10 1 VDD 0.3VDD -30 150 2 0.4 2.8 -23 170 3 2.8
mA mA
4M 8M 4M 8M 4M 8M 4M 8M 4M 8M
uA
mA uA uA V V V V V V V dB mVrms dB V
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W925EP01/ W925EP01FG
DC Electrical Characteristics, continued
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
NOTE
FSK Distortion FSK Output Voltage Port Pull High Resistor RESET pin pull low Resistor Schmitt Input High Threshold Schmitt Input High Threshold Schmitt Hysteresis RNGRC Low Sink Current Input Current Reference Output voltage Reference Output Resistance
FTHD VFD RPH RPL VT+ VTVHYS IRNGL IIN VREF RREF
RL = 5K, VDD = 2.5-3.8 RL = 5K
75 100 100
150 450 170 0.2
-30 170 1000 250 0.68VAD 0.48VAD
dB mVrms K K V V V mA
RNGDI, RNGRC RNGDI, RNGRC RNGDI, RNGRC RNGRC INPx, INNx, RNGDI VREF VREF
0.48VAD 0.28VAD
2.5 0.5VAD - 4% 1 0.5VAD + 4% 2
uA V K No load
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
8.4 Electrical Characteristics - Gain Control OP-Amplifier
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
(Electrical characteristics supersede the recommended operating conditions unless otherwise stated.)
Input Leakage Current Input Resistance Input Offset Voltage Power Supply Rejection Ratio Maximum (GCFBx) Capacitive Load
IIN RIN VOS PSRR CL RL 50 40 10
1
uA M
VSS VIN VDD
25
mV dB 1 kHz 0.1 Vpp ripple on VDD
100
pF k
Maximum Resistive Load (GCFBx)
Note: "" Typical figure are at VDD = 5V and temperature = 25 are design aids only, not guaranteed and not subject to production testing.
8.5
AC Electrical Characteristics
(AC timing characteristics supersede the recommended operating conditions unless otherwise stated.)
Dual Tone Alert Signal Detection Interface
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Low Tone Frequency High Tone Frequency Frequency Deviation accept Frequency Deviation reject Maximum Input Signal Level Input Sensitivity per tone Reject Signal Level per tone b Positive and negative twist accept Noise Tolerance
Notes:
fL fH 1.1 3.5
2130 2750
Hz Hz % % 0.22 dBm a 3 4 5 5 1, 2
-40 7 SNRTONE 20
-38 -48
dBm dBm dB dB
a. dBm = decibels with a reference power of 1 mW into 600 ohms, 0 dBm = 0.7746 Vrms. b. Twist = 20 log (fH amplitude / fL amplitude). 1. Both tones have the same amplitude. Both tones are at the nominal frequencies. 2. Band limited random noise 300 - 3400 Hz. Present only when tone is present. 3. Range within which tones are accepted. 4. Ranges outside of which tones are rejected. 5. These characteristics are at VDD = 5V and temperature = 25 .
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W925EP01/ W925EP01FG
Dual Tone Alert Signal Detection
PARAMETER CONDITION SYMBOL MIN TYP MAX UNITS NOTES
Alert Signal present detect time Alert Signal absent detect time
ALGR
tDP tDA
0.5 0.1
10 8
MS MS
"" Typical figure are at VDD = 5V and temperature = 25 are design aids only, not guaranteed and not subject to production testing.
FSK Detection Interface
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Frequency Detection Bell 202 Mark (logic 1) Bell 202 Space (logic 0) ITU-T V.23 Mark (logic 1) ITU-T V.23 Space (logic 0) Maximum Input Signal Level Input Sensitivity Transmission Rate Input Noise Tolerance
Notes:
1. Both mark and space have the same amplitude. Both mark and space are at the nominal frequencies. 2. Band limited random noise 300 - 3400 Hz. Present only when FSK signal is present. 3. These characteristics are at VDD = 5V and temperature = 25 .
fMark fSpace fMark fSpace
1188 2178 1280.5 2068.5 -43 1188
1200 2200 1300 2100
1212 2222 1319.5 2131.5 -5.78 dBm dBm Hz
+/- 1 % +/- 1 % +/- 1.5 % +/- 1.5 % 1, 3 1, 2
1200
1212
baud dB
SNRTONE
20
FSK Detection
PARAMETER CONDITION SYMBO L MIN TYP MAX UNITS NOTES
FSK detection enable time Input FSK to FCD high delay Input FSK to FCD low delay Data Ready ACK Time Rate Input FSK to DATA delay Frequency High Time Low Time DCLK to FDR delay
FSKE FCD FDR DATA
tFSK tCP tCA tDR tIDD fDCLK 1201.6 415 415 415 tCH tCL tCRD 8 415 1188 416 1200 1 1202.8 416 416 416
25 25 417 1212 5 1204 417 417 417
MS MS MS US BpS MS Hz US US US 2 2 2 2 2 1
DCLK DCLK, FDR
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
Note : 1. FSK input data rate at 1200 +/- 12 baud.
2. OSCI frequency at 4 MHz +/- 0.1%. "" Typical figure are at VDD = 5V and temperature = 25 are design aids only, not guaranteed and not subject to production testing.
DTMF Decoder
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
INPUT SENSITIVITY PER TONE Positive and negative twist accept Frequency Deviation accept Frequency Deviation reject 3rd Tone Tolerance Noise Tolerance Dial tone Tolerance
Note : 1. signal consists of all DTMF tones.
-29 7 1.5 3.5
1
dBm dB % %
1,2 1,2 1,2 1,2 1,2,3 1,2,3 1,2,4
-16 -12 22
dB dB dB
2. Tone duration is 40mS at least, tone pause duration is 40mS at least. 3. Referenced to the lowest level frequency component in DTMF signal. 4. Referenced to the minimum valid accept level.
DTMF Detection Interface
PARAMETER CONDITION SYMBOL MIN TYP MAX UNITS NOTES
DTMF present detect time DTMF absent detect time DTMF Detected Duration DTMF Signal Ignore Time DTMF Pause Accept Time
Est DTMFD=1 DTMFD=0 DTMFD=1
tFP tFA tDD tDI tDPA
0.5 0.1 40
8 8 20
MS MS MS MS MS
20
"" Typical figure are at VDD = 5V and temperature = 25 are design aids only, not guaranteed and not subject to production testing.
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W925EP01/ W925EP01FG
9. PACKAGE
100L QFP(14x20x2.75mm footprint 4.8mm)
HD D
E
H
E
e
b
c
A2 See Detail F A1 y L L
1
A
Seating Plane
Controlling dimension : Millimeters
Symbol
Dimension in inch
Dimension in mm
Min
0.010 0.101 0.008 0.004 0.547 0.783 0.020 0.746 0.960 0.039
Nom
0.014 0.107 0.012 0.006 0.551 0.787 0.026 0.740 0.976 0.047 0.064
Max
0.018 0.113 0.016 0.008 0.555 0.791 0.032 0.756 0.992 0.055
Min
0.25 2.57 0.20 0.10 13.90 19.90 0.498 18.40 24.40 1.00
Nom
0.35 2.72 0.30 0.15 14.00 20.00 0.65 18.80 24.80 1.20 2.40
Max
0.45 2.87 0.40 0.20 14.10 20.10 0.802 19.20 25.20 1.40
A A A b c D E e H H L L y
1 2
D E
1
0.003 0 7 0
0.08 7
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Publication Release Date: Apr. 10, 2006 Revision A2
W925EP01/ W925EP01FG
10. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 A2
Dec. 6, 2005 Apr. 10, 2006 3
New Create Modify lead-free package number
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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